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ST10F276Z5
16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM
Features

Highly performance 16-bit CPU with DSP functions - 31.25 ns instruction cycle time at 64 MHz max CPU clock - Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator - Enhanced boolean bit manipulations - Single-cycle context switching support On-chip memories - 512 Kbyte Flash memory (32-bit fetch) - 320 Kbyte extension Flash memory (16-bit fetch) - Single voltage Flash memories with erase/program controller and 100 K erasing/programming cycles. - Up to 16 Mbyte linear address space for code and data (5 Mbytes with CAN or I2C) - 2 Kbyte internal RAM (IRAM) - 66 Kbyte extension RAM (XRAM) External bus - Programmable external bus configuration & characteristics for different address ranges - Five programmable chip-select signals - Hold-acknowledge bus arbitration support Interrupt - 8-channel peripheral event controller for single cycle interrupt driven data transfer - 16-priority-level interrupt system with 56 sources, sampling rate down to 15.6ns Timers - Two multi-functional general purpose timer units with 5 timers Two 16-channel capture / compare units Device summary
Package PQFP144 LQFP144 Max CPU frequency 64 MHz 40 MHz
7G_3D
PQFP144 28 x 28 x 3.4mm LQFP144 20 x 20 x 1.4mm

4-channel PWM unit + 4-channel XPWM
A/D converter - 24-channel 10-bit - 3 s minimum conversion time Serial channels - Two synchronous/asynchronous serial channels - Two high-speed synchronous channels - One I2C standard interface 2 CAN 2.0B interfaces operating on 1 or 2 CAN busses (64 or 2x32 message, C-CAN version)
Fail-safe protection - Programmable watchdog timer - Oscillator watchdog On-chip bootstrap loader
Clock generation - On-chip PLL with 4 to 12 MHz oscillator - Direct or prescaled clock input Real-time clock and 32 kHz on-chip oscillator
Up to 111 general purpose I/O lines - Individually programmable as input, output or special function - Programmable threshold (hysteresis) Idle, Power-down and Standby modes
Single voltage supply: 5 V 10% (embedded regulator for 1.8 V core supply)
Temperature range (C) -40/+125 -40/+125
Table 1.
Order code ST10F276Z5Q3 ST10F276Z5T3
Iflash 512 Kbytes
Xflash
RAM 68KB
320 Kbytes 512 Kbytes 68KB
December 2007
Rev 2
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www.st.com 1
Contents
ST10F276Z5
Contents
1 2 3 4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 4.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2.1 4.2.2 4.2.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 4.4
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.1 Power supply drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9 4.4.10 4.4.11 4.4.12 Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 XFlash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.5
Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Flash non volatile write protection X register low . . . . . . . . . . . . . . . . . . 38 Flash non volatile write protection X register high . . . . . . . . . . . . . . . . . 39 Flash non volatile write protection I register low . . . . . . . . . . . . . . . . . . 39 Flash non volatile write protection I register high . . . . . . . . . . . . . . . . . . 39 Flash non volatile access protection register 0 . . . . . . . . . . . . . . . . . . . 40
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ST10F276Z5 4.5.7 4.5.8 4.5.9 4.5.10 4.5.11
Contents Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . 40 Flash non volatile access protection register 1 high . . . . . . . . . . . . . . . 41 Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.6 4.7
Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5
Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.1 5.2 Selection among user-code, standard or alternate bootstrap . . . . . . . . . 47 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 Entering the standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . 48 ST10 configuration in BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Booting steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Hardware to activate BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Memory configuration in bootstrap loader mode . . . . . . . . . . . . . . . . . . 52 Loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Exiting bootstrap loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3
Standard bootstrap with UART (RS232 or K-Line) . . . . . . . . . . . . . . . . . . 54
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Entering bootstrap via UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ST10 Configuration in UART BSL (RS232 or K-Line) . . . . . . . . . . . . . . 56 Loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Choosing the baud rate for the BSL via UART . . . . . . . . . . . . . . . . . . . 57
5.4
Standard bootstrap with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Entering the CAN bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Loading the start-up code via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Choosing the baud rate for the BSL via CAN . . . . . . . . . . . . . . . . . . . . 61 Computing the baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Bootstrap via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.5
Comparing the old and the new bootstrap loader . . . . . . . . . . . . . . . . . . 65
5.5.1 5.5.2 Software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Hardware aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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Contents
ST10F276Z5
5.6
Alternate boot mode (ABM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.6.10 5.6.11 5.6.12 Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . 67 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Exiting alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Alternate boot user software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 User/alternate mode signature integrity check . . . . . . . . . . . . . . . . . . . 68 Alternate boot user software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 68 EMUCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Internal decoding of test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.7
Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6
Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1 6.2 6.3 Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 MAC coprocessor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7 8
External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8.1 8.2 X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9 10
Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.1 10.2 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11 12
PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.1 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 I/Os special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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ST10F276Z5 12.2.1 12.2.2
Contents Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.3
Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
13 14
A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.1 14.2 14.3 14.4 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 96 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 98
15 16
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
16.1 16.2 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
17 18 19
Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
20
Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
20.1 20.2 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
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Contents 20.2.1 20.2.2
ST10F276Z5 Protected Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Interruptible Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
20.3
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
20.3.1 20.3.2 20.3.3 20.3.4 Entering Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Exiting Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Real-time clock and Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
21 22
Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 Register description format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Special function registers ordered by name . . . . . . . . . . . . . . . . . . . . . 141 Special function registers ordered by address . . . . . . . . . . . . . . . . . . . . 148 X-registers sorted by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 X-registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Flash registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
22.10.1 XPERCON and XPEREMU registers . . . . . . . . . . . . . . . . . . . . . . . . . 176
22.10 System configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 22.11 Emulation dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
23
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
23.1 23.2 23.3 23.4 23.5 23.6 23.7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
23.7.1 23.7.2 23.7.3 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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ST10F276Z5 23.7.4 23.7.5 23.7.6
Contents Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Analog input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Example of external network sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
23.8
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
23.8.1 23.8.2 23.8.3 23.8.4 23.8.5 23.8.6 23.8.7 23.8.8 23.8.9 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 PLL Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
23.8.10 Jitter in the input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 23.8.11 Noise in the PLL loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 23.8.12 PLL lock/unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 23.8.13 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 23.8.14 32 kHz Oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 23.8.15 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 23.8.16 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 23.8.17 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 23.8.18 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 23.8.19 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 23.8.20 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 23.8.21 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 23.8.22 High-speed synchronous serial interface (SSC) timing modes . . . . . . 224
24
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
24.1 Functional limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
24.1.1 24.1.2 24.1.3 24.1.4 24.1.5 24.1.6 Injected conversion stalling the A/D converter . . . . . . . . . . . . . . . . . . . 228 Concurrent transmission requests in DAR-mode (C-CAN module) . . . 231 Disabling the transmission requests (C-CAN module) . . . . . . . . . . . . . 231 Spurious BREQ pulse in slave mode during external bus arbitration phase 232 Executing PWRDN instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Behavior of CAPCOM outputs in COMPARE mode 3 . . . . . . . . . . . . . 233
24.2
Electrical limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
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Contents
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25 26
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
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ST10F276Z5
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Flash modules absolute mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Flash modules sectorization (read operations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Flash modules sectorization (write operations or with roms1='1') . . . . . . . . . . . . . . . . . . . 27 Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Banks (BxS) and sectors (BxFy) status bits meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash data register 0 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash data register 1 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 XFlash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Flash non volatile write protection X register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Flash non volatile write protection X register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Flash non volatile write protection I register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Flash non volatile write protection I register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Flash non volatile access protection register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Flash non volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ST10F276Z5 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ST10 configuration in BSL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ST10 configuration in UART BSL mode (RS232 or K-line). . . . . . . . . . . . . . . . . . . . . . . . . 56 ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 BRP and PT0 values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Software topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Hardware topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ABM bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Selective boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 84 CAPCOM timer input frequencies, resolutions and periods at 64 MHz . . . . . . . . . . . . . . . 84 GPT1 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 85 GPT1 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 86
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101.
ST10F276Z5
GPT2 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 87 GPT2 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 87 PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 89 PWM unit frequencies and resolutions at 64 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 90 ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . 96 ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . 97 ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . . 97 ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . . 98 Synchronous baud rate and reload values (fCPU = 40 MHz). . . . . . . . . . . . . . . . . . . . . . . 99 Synchronous baud rate and reload values (fCPU = 64 MHz). . . . . . . . . . . . . . . . . . . . . . . 99 WDTREL reload value (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 WDTREL reload value (fCPU = 64 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 130 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 General purpose registers (GPRs) bytewise addressing. . . . . . . . . . . . . . . . . . . . . . . . . 139 Special function registers ordered by address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Special function registers ordered by address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 X-Registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 X-registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 FLASH registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 MANUF description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 IDCHIP description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 IDMEM description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 IDPROG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Identification register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 SYSCON description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 BUSCON4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 RPOH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 EXIxES bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 EXISEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 EXIxSS and port 2 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 SFR area description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 ESFR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Segment 8 address range mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 A/D Converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 PLL lock/unlock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Negative resistance (absolute min. value @125oC / VDD = 4.5 V) . . . . . . . . . . . . . . . . . 204
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ST10F276Z5 Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112.
List of tables
32 kHz Oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Minimum values of negative resistance (module). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 External clock drive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 PQFP144 - 144-pin Plastic Quad Flatpack 28 x 28 mm, 0.65 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Table 113. LQFP144 - 144 pin low profile quad flat package 20x20mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Table 114. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
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List of figures
ST10F276Z5
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Flash modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ST10F276Z5 new standard bootstrap loader program flow . . . . . . . . . . . . . . . . . . . . . . . . 50 Booting steps for ST10F276Z5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Hardware provisions to activate the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 UART bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Baud rate deviation between host and ST10F276Z5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 CAN bootstrap loader sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Bit rate measurement over a predefined zero-frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Reset boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 CPU Block Diagram (MAC Unit not included). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . 102 Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . 102 Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . 103 Connection to one CAN bus with internal Parallel mode enabled . . . . . . . . . . . . . . . . . . 103 Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Synchronous short / long hardware RESET (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SW / WDT bidirectional RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 SW / WDT bidirectional RESET (EA=0) followed by a HW RESET . . . . . . . . . . . . . . . . . 124 Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 127 Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 128 PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 131 External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 184 A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 192
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ST10F276Z5
List of figures
Figure 49. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Figure 50. Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Figure 51. Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Figure 52. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 53. ST10F276Z5 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Figure 54. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Figure 55. 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Figure 56. External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Figure 57. Multiplexed bus with/without R/W delay and normal ALE. . . . . . . . . . . . . . . . . . . . . . . . . 210 Figure 58. Multiplexed bus with/without R/W delay and extended ALE . . . . . . . . . . . . . . . . . . . . . . . 211 Figure 59. Multiplexed bus, with/without R/W delay, normal ALE, R/W CS. . . . . . . . . . . . . . . . . . . . 212 Figure 60. Multiplexed bus, with/without R/ W delay, extended ALE, R/W CS . . . . . . . . . . . . . . . . . 213 Figure 61. Demultiplexed bus, with/without read/write delay and normal ALE . . . . . . . . . . . . . . . . . 216 Figure 62. Demultiplexed bus with/without R/W delay and extended ALE . . . . . . . . . . . . . . . . . . . . 217 Figure 63. Demultiplexed bus with ALE and R/W CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Figure 64. Demultiplexed bus, no R/W delay, extended ALE, R/W CS . . . . . . . . . . . . . . . . . . . . . . . 219 Figure 65. CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Figure 66. External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Figure 67. External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Figure 68. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Figure 69. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 70. ADC injection theoretical operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Figure 71. ADC injection actual operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Figure 72. Connecting an ST10 in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Figure 73. PQFP144 - 144-pin plastic Quad Flatpack 28 x 28 mm, 0.65 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Figure 74. LQFP144 - 144 pin low profile quad flat package 20x20 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
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Description
ST10F276Z5
1
Description
The ST10F276Z5 is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 32 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL. The ST10F276Z5 is processed in 0.18 m CMOS technology. The MCU core and the logic is supplied with a 5 to 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V supply and I/Os work at 5 V. The device is upward compatible with the ST10F269 device, with the following set of differences:
Flash control interface is now based on STMicroelectronics third generation of standalone Flash memories (M29F400 series), with an embedded Program/Erase Controller. This completely frees up the CPU during programming or erasing the Flash. Only one supply pin (ex DC1 in ST10F269, renamed into V18) on the QFP144 package is used for decoupling the internally generated 1.8 V core logic supply. Do not connect this pin to 5.0 V external supply. Instead, this pin should be connected to a decoupling capacitor (ceramic type, typical value 10 nF, maximum value 100 nF). The AC and DC parameters are modified due to a difference in the maximum CPU frequency. A new VDD pin replaces DC2 of ST10F269. EA pin assumes a new alternate functionality: it is also used to provide a dedicated power supply (see VSTBY) to maintain biased a portion of the XRAM (16Kbytes) when the main Power Supply of the device (VDD and consequently the internally generated V18) is turned off for low power mode, allowing data retention. VSTBY voltage shall be in the range 4.5-5.5 V, and a dedicated embedded low power voltage regulator is in charge to provide the 1.8 V for the RAM, the low-voltage section of the 32 kHz oscillator and the real-time clock module when not disabled. It is allowed to exceed the upper limit up to 6 V for a very short period of time during the global life of the device, and exceed the lower limit down to 4 V when RTC and 32 kHz on-chip oscillator are not used. A second SSC mapped on the XBUS is added (SSC of ST10F269 becomes here SSC0, while the new one is referred as XSSC or simply SSC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic SSC, and the new XSSC. A second ASC mapped on the XBUS is added (ASC0 of ST10F269 remains ASC0, while the new one is referred as XASC or simply as ASC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic ASC, and the new XASC. A second PWM mapped on the XBUS is added (PWM of ST10F269 becomes here PWM0, while the new one is referred as XPWM or simply as PWM1). Note that some

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ST10F276Z5
Description restrictions and functional differences due to the XBUS peculiarities are present between the classic PWM, and the new XPWM.

An I2C interface on the XBUS is added (see X-I2C or simply I2C interface). CLKOUT function can output either the CPU clock (like in ST10F269) or a software programmable prescaled value of the CPU clock. Embedded memory size has been significantly increased (both Flash and RAM). PLL multiplication factors have been adapted to new frequency range. A/D Converter is not fully compatible versus ST10F269 (timing and programming model). Formula for the conversion time is still valid, while the sampling phase programming model is different. Besides, additional 8 channels are available on P1L pins as alternate function: the accuracy reachable with these extra channels is reduced with respect to the standard Port5 channels. External Memory bus potential limitations on maximum speed and maximum capacitance load could be introduced (under evaluation): ST10F276Z5 will probably not be able to address an external memory at 64 MHz with 0 wait states (under evaluation). XPERCON register bit mapping modified according to new peripherals implementation (not fully compatible with ST10F269). Bond-out chip for emulation (ST10R201) cannot achieve more than 50 MHz at room temperature (so no real-time emulation possible at maximum speed). Input section characteristics are different. The threshold programmability is extended to all port pins (additional XPICON register); it is possible to select standard TTL (with up to 500 mV of hysteresis) and standard CMOS (with up to 800 mV of hysteresis). Output transition is not programmable. CAN module is enhanced: the ST10F276Z5 implements two C-CAN modules, so the programming model is slightly different. Besides, the possibility to map in parallel the two CAN modules is added (on P4.5/P4.6). On-chip main oscillator input frequency range has been reshaped, reducing it from 125 MHz down to 4-12 MHz. This is a high performance oscillator amplifier, providing a very high negative resistance and wide oscillation amplitude: when this on-chip amplifier is used as reference for real-time clock module, the power-down consumption is dominated by the consumption of the oscillator amplifier itself. A metal option is added to offer a low power oscillator amplifier working in the range of 4-8 MHz: this will allow a power consumption reduction when real-time clock is running in Power-down mode using as reference the on-chip main oscillator clock. A second on-chip oscillator amplifier circuit (32 kHz) is implemented for low power modes: it can be used to provide the reference to the real-time clock counter (either in Power-down or Standby mode). Pin XTAL3 and XTAL4 replace a couple of VDD/VSS pins of ST10F269. Possibility to re-program internal XBUS chip select window characteristics (XRAM2 and XFLASH address window) is added.

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Description Figure 1. Logic symbol
ST10F276Z5
V18 VDD VSS XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT VAREF VAGND NMI EA / VSTBY READY ALE RD WR / WRL Port 5 16-bit Port 0 16-bit Port 1 16-bit Port 2 16-bit
ST10F276Z5
Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit RPD
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ST10F276Z5
Pin data
2
Pin data
Figure 2. Pin configuration (top view)
XTAL4 XTAL3 NMI RSTOUT RSTIN VSS XTAL1 XTAL2 VDD P1H.7 / A15 / CC27I P1H.6 / A14 / CC26I P1H.5 / A13 / CC25I P1H.4 / A12 / CC24I P1H.3 / A11 P1H.2 / A10 P1H.1 / A9 P1H.0 / A8 VSS VDD P1L.7 / A7 / AN23 (*) P1L.6 / A6 / AN22 (*) P1L.5 / A5 / AN21 (*) P1L.4 / A4 / AN20 (*) P1L.3 / A3 / AN19 (*) P1L.2 / A2 / AN18 (*) P1L.1 / A1 / AN17 (*) P1L.0 / A0 / AN16 (*) P0H.7 / AD15 P0H.6 / AD14 P0H.5 / AD13 P0H.4 / AD12 P0H.3 / AD11 P0H.2 / AD10 P0H.1 / AD9 VSS VDD 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
P6.0 / CS0 P6.1 / CS1 P6.2 / CS2 P6.3 / CS3 P6.4 / CS4 P6.5 / HOLD / SCLK1 P6.6 / HLDA / MTSR1 P6.7 / BREQ / MRST1 P8.0 / XPOUT0 / CC16IO P8.1 / XPOUT1 / CC17IO P8.2 / XPOUT2 / CC18IO P8.3 / XPOUT3 / CC19IO P8.4 / CC20IO P8.5 / CC21IO P8.6 / RxD1 / CC22IO P8.7 / TxD1 / CC23IO VDD VSS P7.0 / POUT0 P7.1 / POUT1 P7.2 / POUT2 P7.3 / POUT3 P7.4 / CC28IO P7.5 / CC29IO P7.6 / CC30IO P7.7 / CC31IO P5.0 / AN0 P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4 P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
ST10F276Z5
P0H.0 / AD8 P0L.7 / AD7 P0L.6 / AD6 P0L.5 / AD5 P0L.4 / AD4 P0L.3 / AD3 P0L.2 / AD2 P0L.1 / AD1 P0L.0 / AD0 EA / VSTBY ALE READY WR/WRL RD VSS VDD P4.7 / A23 / CAN2_TxD / SDA P4.6 / A22 / CAN1_TxD / CAN2_TxD P4.5 / A21 / CAN1_RxD / CAN2_RxD P4.4 / A20 / CAN2_RxD / SCL P4.3 / A19 P4.2 / A18 P4.1 / A17 P4.0 / A16 RPD VSS VDD P3.15 / CLKOUT P3.13 / SCLK0 P3.12 / BHE / WRH P3.11 / RxD0 P3.10 / TxD0 P3.9 / MTSR0 P3.8 / MRST0 P3.7 / T2IN P3.6 / T3IN
VAREF VAGND P5.10 / AN10 / T6EUD P5.11 / AN11 / T5EUD P5.12 / AN12 / T6IN P5.13 / AN13 / T5IN P5.14 / AN14 / T4EUD P5.15 / AN15 / T2EUD VSS VDD P2.0 / CC0IO P2.1 / CC1IO P2.2 / CC2IO P2.3 / CC3IO P2.4 / CC4IO P2.5 / CC5IO P2.6 / CC6IO P2.7 / CC7IO VSS V18 P2.8 / CC8IO / EX0IN P2.9 / CC9IO / EX1IN P2.10 / CC10IO / EX2IN P2.11 / CC11IO / EX3IN P2.12 / CC12IO / EX4IN P2.13 / CC13IO / EX5IN P2.14 / CC14IO / EX6IN P2.15 / CC15IO / EX7IN / T7IN P3.0 / T0IN P3.1 / T6OUT P3.2 / CAPIN P3.3 / T3OUT P3.4 / T3EUD P3.5 / T4IN VSS VDD
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
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Pin data Table 2.
Symbol
ST10F276Z5 Pin description
Pin Type Function 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The following Port 6 pins have alternate functions: P6.0 ... P6.4 P6.5 CS0 ... CS4 HOLD SCLK1 P6.6 HLDA MTSR1 P6.7 BREQ MRST1 Chip select 0 output ... Chip select 4 output External master hold request input SSC1: master clock output / slave clock input Hold acknowledge output SSC1: master-transmitter / slave-receiver O/I Bus request output SSC1: master-receiver / slave-transmitter I/O
1-8
I/O
1 ... P6.0 - P6.7 5 6
O ... O I I/O O
7 I/O O 8 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 8 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS). The following Port 8 pins have alternate functions: P8.0 CC16IO XPWM0 ... P8.3 ... CC19IO XPWM0 P8.4 P8.5 P8.6 CC20IO CC21IO CC22IO RxD1 P8.7 CC23IO TxD1 CAPCOM2: CC16 capture input / compare output PWM1: channel 0 output ... CAPCOM2: CC19 capture input / compare output PWM1: channel 3 output CAPCOM2: CC20 capture input / compare output CAPCOM2: CC21 capture input / compare output CAPCOM2: CC22 capture input / compare output ASC1: Data input (Asynchronous) or I/O (Synchronous) CAPCOM2: CC23 capture input / compare output ASC1: Clock / Data output (Asynchronous/Synchronous)
9-16
I/O
I/O 9 O ... P8.0 - P8.7 12 O 13 14 15 I/O I/O 16 O I/O I/O I/O ... I/O
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ST10F276Z5 Table 2.
Symbol
Pin data
Pin description (continued)
Pin Type Function 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS). The following Port 7 pins have alternate functions: P7.0 ... P7.3 P7.4 ... P7.7 POUT0 ... POUT3 CC28IO ... CC31IO PWM0: channel 0 output ... PWM0: channel 3 output CAPCOM2: CC28 capture input / compare output ... CAPCOM2: CC31 capture input / compare output
19-26
I/O
19 P7.0 - P7.7 ... 22 23 ... 26
O ... O I/O ... I/O
27-36 39-44
I I
16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can be the analog input channels (up to 16) for the A/D converter, where P5.x equals ANx (Analog input channel x), or they are timer inputs. The input threshold of Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate functions: P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 T6EUD T5EUD T6IN T5IN T4EUD T2EUD GPT2: timer T6 external up/down control input GPT2: timer T5 external up/down control input GPT2: timer T6 count input GPT2: timer T5 count input GPT1: timer T4 external up/down control input GPT1: timer T2 external up/down control input
P5.0 - P5.9 P5.10 - P5.15
39 40 41 42 43 44
I I I I I I
47-54 57-64
I/O
16-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 2 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS). The following Port 2 pins have alternate functions: P2.0 ... P2.7 P2.8 CC0IO ... CC7IO CC8IO EX0IN ... P2.15 ... CC15IO EX7IN T7IN CAPCOM: CC0 capture input/compare output ... CAPCOM: CC7 capture input/compare output CAPCOM: CC8 capture input/compare output Fast external interrupt 0 input ... CAPCOM: CC15 capture input/compare output Fast external interrupt 7 input CAPCOM2: timer T7 count input
47 ... P2.0 - P2.7 P2.8 - P2.15 54 57
I/O ... I/O I/O I
... 64
... I/O I I
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Pin data Table 2.
Symbol
ST10F276Z5 Pin description (continued)
Pin 65-70, 73-80, 81 65 66 67 68 69 Type I/O I/O I/O I O I O I I I I I/O I/O O I/O O Function 15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 3 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or CMOS). The following Port 3 pins have alternate functions: P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 T0IN T6OUT CAPIN T3OUT T3EUD T4IN T3IN T2IN MRST0 MTSR0 TxD0 RxD0 BHE WRH 80 81 I/O O P3.13 P3.15 SCLK0 CLKOUT CAPCOM1: timer T0 count input GPT2: timer T6 toggle latch output GPT2: register CAPREL capture input GPT1: timer T3 toggle latch output GPT1: timer T3 external up/down control input GPT1; timer T4 input for count/gate/reload/capture GPT1: timer T3 count/gate input GPT1: timer T2 input for count/gate/reload / capture SSC0: master-receiver/slave-transmitter I/O SSC0: master-transmitter/slave-receiver O/I ASC0: clock / data output (asynchronous/synchronous) ASC0: data input (asynchronous) or I/O (synchronous) External memory high byte enable signal External memory high byte write strobe SSC0: master clock output / slave clock input System clock output (programmable divider on CPU clock)
P3.0 - P3.5 P3.6 - P3.13, P3.15
70 73 74 75 76 77 78 79
20/239
ST10F276Z5 Table 2.
Symbol
Pin data
Pin description (continued)
Pin Type Function Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold is selectable (TTL or CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured as push-pull or open drain drivers. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 P4.1 P4.2 P4.3 P4.4 A16 A17 A18 A19 A20 CAN2_RxD SCL P4.5 A21 CAN1_RxD CAN2_RxD P4.6 A22 CAN1_TxD CAN2_TxD P4.7 A23 CAN2_TxD SDA Segment address line Segment address line Segment address line Segment address line Segment address line CAN2: receive data input I2C Interface: serial clock Segment address line CAN1: receive data input CAN2: receive data input Segment address line CAN1: transmit data output CAN2: transmit data output Most significant segment address line CAN2: transmit data output I2C Interface: serial data
85-92
I/O
85 86 87 88 89 P4.0 -P4.7
O O O O O I I/O
90
O I I
91
O O O
92
O O I/O
RD
95
O
External memory read strobe. RD is activated for every external instruction or data read access. External memory write strobe. In WR-mode this pin is activated for every external data write access. In WRL mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection. Ready input. The active level is programmable. When the ready function is enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of waitstate cycles until the pin returns to the selected active level. Address latch enable output. In case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines.
WR/WRL
96
O
READY/ READY
97
I
ALE
98
O
21/239
Pin data Table 2.
Symbol
ST10F276Z5 Pin description (continued)
Pin Type Function External access enable pin. A low level applied to this pin during and after Reset forces the ST10F276Z5 to start the program from the external memory space. A high level forces the ST10F276Z5 to start in the internal memory space. This pin is also used (when Standby mode is entered, that is the device under reset and main VDD turned off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference voltage for the low-power embedded voltage regulator which generates the internal 1.8 V supply for the RTC module (when not disabled) and to retain data inside the Standby portion of the XRAM (16Kbyte). It can range from 4.5 to 5.5 V (6 V for a reduced amount of time during the device life, 4.0 V when RTC and 32 kHz on-chip oscillator amplifier are turned off). In running mode, this pin can be tied low during reset without affecting 32 kHz oscillator, RTC and XRAM activities, since the presence of a stable VDD guarantees the proper biasing of all those modules. Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold of Port 0 is selectable (TTL or CMOS). In case of an external bus configuration, PORT0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes
EA / VSTBY
99
I
P0L.0 -P0L.7, 100-107, P0H.0 108, P0H.1 - P0H.7 111-117
I/O
Data path width P0L.0 - P0L.7: P0H.0 - P0H.7:
8-bit D0 - D7 I/O
16-bi D0 - D7 D8 - D15
Multiplexed bus modes Data path width P0L.0 - P0L.7: P0H.0 - P0H.7: 8-bit AD0 - AD7
A8 - A15
16-bi AD0 - AD7
AD8 - AD15
118-125 128-135 P1L.0 - P1L.7 P1H.0 - P1H.7
I/O
Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes: if at least BUSCONx is configured such the demultiplexed mode is selected, the pis of PORT1 are not available for general purpose I/O function. The input threshold of Port 1 is selectable (TTL or CMOS). The pins of P1L also serve as the additional (up to 8) analog input channels for the A/D converter, where P1L.x equals ANy (Analog input channel y, where y = x + 16). This additional function have higher priority on demultiplexed bus function. The following PORT1 pins have alternate functions: P1H.4 CC24IO P1H.5 CC25IO P1H.6 CC26IO P1H.7 CC27IO CAPCOM2: CC24 capture input CAPCOM2: CC25 capture input CAPCOM2: CC26 capture input CAPCOM2: CC27 capture input
132 133 134 135
I I I I
22/239
ST10F276Z5 Table 2.
Symbol XTAL1 XTAL2
Pin data
Pin description (continued)
Pin 138 137 Type I O Function XTAL1 Main oscillator amplifier circuit and/or external clock input. XTAL2 Main oscillator amplifier circuit output. To clock the device from an external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum high / low and rise / fall times specified in the AC Characteristics must be observed.
XTAL3 XTAL4
143 144
I O
XTAL3 32 kHz oscillator amplifier circuit input XTAL4 32 kHz oscillator amplifier circuit output When 32 kHz oscillator amplifier is not used, to avoid spurious consumption, XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32 in RTCCON register shall be set. 32 kHz oscillator can only be driven by an external crystal, and not by a different clock source. Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the device. An internal pull-up resistor permits power-on reset using only a capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of the internal reset sequence. Internal Reset Indication Output. This pin is driven to a low level during hardware, software or watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = `0' in SYSCON register, when the PWRDN (Power-down) instruction is executed, the NMI pin must be low in order to force the device to go into Power-down mode. If NMI is high and PWDCFG ='0', when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. A/D converter reference voltage and analog supply A/D converter reference and analog ground Timing pin for the return from interruptible Power-down mode and synchronous / asynchronous reset selection. Digital supply voltage = + 5 V during normal operation, idle and Power-down modes. It can be turned off when Standby RAM mode is selected.
RSTIN
140
I
RSTOUT
141
O
NMI
142
I
VAREF VAGND RPD
37 38 84 17, 46, 72,82,93, 109, 126, 136 18,45, 55,71, 83,94, 110, 127, 139 56
-
VDD
-
VSS
-
Digital ground
V18
-
1.8 V decoupling pin: a decoupling capacitor (typical value of 10 nF, max 100 nF) must be connected between this pin and nearest VSS pin.
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Functional description
ST10F276Z5
3
Functional description
The ST10F276Z5 architecture combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F276Z5. Figure 3. Block diagram
16 XFLASH 320K 16 IFLASH 512K 32 CPU-Core and MAC Unit 16 IRAM 2K
XRAM 48K
16 16 XRTC 16 PEC Oscillator 32kHz Oscillator Interrupt Controller PLL 5 V-1.8 V Voltage Regulator 16 Watchdog
XRAM 16 16K (STBY) 16 XPWM XRAM 16 16 2K XASC (PEC) 16 16 XI2C XSSC 16 16 XCAN1 XCAN2
Port 0
16
GPT1 / GPT2
External Bus Controller
CAPCOM2
Port 1
Port 4
8
BRG
BRG
Port 6 8
Port 5 16
Port 3 15
Port 7 8
Port 8 8
24/239
Port 2
16
CAPCOM1
10-bit ADC
ASC0
SSC0
PWM
16
ST10F276Z5
Internal Flash memory
4
4.1
Internal Flash memory
Overview
The on-chip Flash is composed by two matrix modules each one containing one array divided in two banks that can be read and modified independently one of the other: one bank can be read while another bank is under modification. Figure 4. Flash modules structure
IFLASH (Module I) Bank 1: 128 Kbyte program memory Control section HV and Ref. generator XFLASH (Module X) Bank 3: 128 Kbyte program memory
Bank 0: 384 Kbyte program memory + 8 Kbyte test-Flash
Program/erase controller
Bank 2: 192 Kbyte program memory
I-BUS interface
X-BUS interface
The write operations of the 4 banks are managed by an embedded Flash program/erase controller (FPEC). The high voltages needed for program/erase operations are internally generated. The data bus is 32-bit wide. Due to ST10 core architecture limitation, only the first 512 Kbytes are accessed at 32-bit (internal Flash bus, see I-BUS), while the remaining 320 Kbytes are accessed at 16-bit (see X-BUS).
4.2
4.2.1
Functional description
Structure
The following table shows the address space reserved to the Flash module. Table 3. Flash modules absolute mapping
Description IFLASH sectors XFLASH sectors Registers and Flash internal reserved area Addresses 0x00 0000 to 0x08 FFFF 0x09 0000 to 0x0D FFFF 0x0E 0000 to 0x0E FFFF Size 512 Kbyte 320 Kbyte 64 Kbyte
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Internal Flash memory
ST10F276Z5
4.2.2
Modules structure
The IFLASH module is composed by 2 banks. Bank 0 contains 384 Kbyte of program memory divided in 10 sectors. Bank 0 contains also a reserved sector named test-Flash. Bank 1 contains 128 Kbyte of program memory or parameter divided in 2 sectors (64 Kbyte each). The XFLASH module is composed by 2 banks as well. Bank 2 contains 192 Kbyte of Program Memory divided in 3 sectors. Bank 3 contains 128 Kbyte of program memory or parameter divided in 2 sectors (64 Kbyte each). Addresses from 0x0E 0000 to 0x0E FFFF are reserved for the control register interface and other internal service memory space used by the Flash program/erase controller. The following tables show the memory mapping of the Flash when it is accessed in read mode (Table 4), and when accessed in write or erase mode (Table 3): note that with this second mapping, the first three banks are remapped into code segment 1 (same as obtained when setting bit ROMS1 in SYSCON register). Table 4.
Bank
Flash modules sectorization (read operations)
Description Bank 0 Flash 0 (B0F0) Bank 0 Flash 1 (B0F1) Bank 0 Flash 2 (B0F2) Bank 0 Flash 3 (B0F3) Bank 0 Flash 4 (B0F4) Addresses 0x0000 0000 - 0x0000 1FFF 0x0000 2000 - 0x0000 3FFF 0x0000 4000 - 0x0000 5FFF 0x0000 6000 - 0x0000 7FFF 0x0001 8000 - 0x0001 FFFF 0x0002 0000 - 0x0002 FFFF 0x0003 0000 - 0x0003 FFFF 0x0004 0000 - 0x0004 FFFF 0x0005 0000 - 0x0005 FFFF 0x0006 0000 - 0x0006 FFFF 0x0007 0000 - 0x0007 FFFF 0x0008 0000 - 0x0008 FFFF 0x0009 0000 - 0x0009 FFFF 0x000A 0000 - 0x000A FFFF 0x000B 0000 - 0x000B FFFF 0x000C 0000 - 0x000C FFFF 0x000D 0000 - 0x000D FFFF Size 8 KB 8 KB 8 KB 8 KB 32 KB 64 KB 32-bit (I-BUS) Bank 0 Flash 6 (B0F6) Bank 0 Flash 7 (B0F7) Bank 0 Flash 8 (B0F8) Bank 0 Flash 9 (B0F9) Bank 1 Flash 0 (B1F0) 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 16-bit (X-BUS) ST10 bus size
B0 Bank 0 Flash 5 (B0F5)
B1 Bank 1 Flash 1 (B1F1) Bank 2 Flash 0 (B2F0) B2 Bank 2 Flash 1 (B2F1) Bank 2 Flash 2 (B2F2) Bank 3 Flash 0 (B3F0) B3 Bank 3 Flash 1 (B3F1)
26/239
ST10F276Z5 Table 5.
Bank
Internal Flash memory Flash modules sectorization (write operations or with roms1='1')
Description Bank 0 Test-Flash (B0TF) Bank 0 Flash 0 (B0F0) Bank 0 Flash 1 (B0F1) Bank 0 Flash 2 (B0F2) Bank 0 Flash 3 (B0F3) B0 Bank 0 Flash 4 (B0F4) Bank 0 Flash 5 (B0F5) Bank 0 Flash 6 (B0F6) Bank 0 Flash 7 (B0F7) Bank 0 Flash 8 (B0F8) Bank 0 Flash 9 (B0F9) Bank 1 Flash 0 (B1F0) B1 Bank 1 Flash 1 (B1F1) Bank 2 Flash 0 (B2F0) B2 Bank 2 Flash 1 (B2F1) Bank 2 Flash 2 (B2F2) Bank 3 Flash 0 (B3F0) B3 Bank 3 Flash 1 (B3F1) 0x000D 0000 - 0x000D FFFF 64 KB 0x0008 0000 - 0x0008 FFFF 0x0009 0000 - 0x0009 FFFF 0x000A 0000 - 0x000A FFFF 0x000B 0000 - 0x000B FFFF 0x000C 0000 - 0x000C FFFF 64 KB 64 KB 64 KB 64 KB 64 KB 16-bit (X-BUS) Addresses 0x0000 0000 - 0x0000 1FFF 0x0001 0000 - 0x0001 1FFF 0x0001 2000 - 0x0001 3FFF 0x0001 4000 - 0x0001 5FFF 0x0001 6000 - 0x0001 7FFF 0x0001 8000 - 0x0001 FFFF 0x0002 0000 - 0x0002 FFFF 0x0003 0000 - 0x0003 FFFF 0x0004 0000 - 0x0004 FFFF 0x0005 0000 - 0x0005 FFFF 0x0006 0000 - 0x0006 FFFF 0x0007 0000 - 0x0007 FFFF Size 8 KB 8 KB 8 KB 8 KB 8 KB 32 KB 64 KB 32-bit (I-BUS) 64 KB 64 KB 64 KB 64 KB 64 KB ST10 Bus size
The table above refers to the configuration when bit ROMS1 of SYSCON register is set. When Bootstrap mode is entered:

Test-Flash is seen and available for code fetches (address 00'0000h) User IFlash is only available for read and write accesses Write accesses must be made with addresses starting in segment 1 from 01'0000h, whatever ROMS1 bit in SYSCON value Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.
In Bootstrap mode, by default ROMS1 = 0, so the first 32KBytes of IFlash are mapped in segment 0. Example: In default configuration, to program address 0, user must put the value 01'0000h in the FARL and FARH registers, but to verify the content of the address 0 a read to 00'0000h must be performed. Table 6 shows the control register interface composition: this set of registers can be addressed by the CPU.
27/239
Internal Flash memory Table 6.
Bank FCR1-0 FDR1-0 FAR FER FNVWPXR FNVWPIR FNVAPR0 FNVAPR1 XFICR
ST10F276Z5 Control register interface
Description Flash control registers 1-0 Flash data registers 1-0 Flash address registers Flash error register Flash non volatile protection X register Flash non volatile protection I register Flash non volatile access protection register 0 Flash non volatile access protection register 1 XFlash interface control register Addresses 0x000E 0000 - 0x000E 0007 0x000E 0008 - 0x000E 000F 0x000E 0010 - 0x000E 0013 0x000E 0014 - 0x000E 0015 0x000E DFB0 - 0x000E DFB3 0x000E DFB4 - 0x000E DFB7 0x000E DFB8 - 0x000E DFB9 0x000E DFBC - 0x000E DFBF 0x000E E000 - 0x000E E001 Size 8 byte 8 byte 4 byte 2 byte 4 byte 4 byte 2 byte 4 byte 2 byte 16-bit (X-BUS) ST10 bus size
4.2.3
Low power mode
The Flash modules are automatically switched off executing PWRDN instruction. The consumption is drastically reduced, but exiting this state can require a long time (tPD).
Note:
Recovery time from Power-down mode for the Flash modules is anyway shorter than the main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash, it is important to size properly the external circuit on RPD pin. Power-off Flash mode is entered only at the end of the eventually running Flash write operation.
4.3
Write operation
The Flash modules have one single register interface mapped in the memory space of the XFlash module (0x0E 0000 to 0x0E 0013). All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16bit registers are used to store Flash Address and Data for Program operations (FARH/L and FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible with 8 and 16-bit instructions (since mapped on ST10 XBUS).
Note:
Before accessing the XFlash module (and consequently also the Flash register to be used for program/erasing operations), bit XFLASHEN in XPERCON register and bit XPEN in SYSCON register shall be set. The 4 Banks have their own dedicated sense amplifiers, so that any Bank can be read while any other Bank is written. However simultaneous write operations ("write" means either Program or Erase) on different Banks are forbidden: when there is a write operation on going (Program or Erase) anywhere in the Flash, no other write operation can be performed. During a Flash write operation any attempt to read the bank under modification will output invalid data (software trap 009Bh). This means that the Flash Bank is not fetchable when a write operation is active: the write operation commands must be executed from another
28/239
ST10F276Z5
Internal Flash memory
Bank, or from the other module or again from another memory (internal RAM or external memory). Note: During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the Flash Control Registers.
4.3.1
Power supply drop
If during a write operation the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the modules are reset to Read mode. At following Power-on, an interrupted Flash write operation must be repeated.
4.4
4.4.1
Registers description
Flash control register 0 low
The Flash control register 0 low (FCR0L) together with the Flash control register 0 high (FCR0H) is used to enable and to monitor all the write operations for both the Flash modules. The user has no access in write mode to the test-Flash (B0TF). Besides, testFlash block is seen by the user in Bootstrap mode only.
FCR0L (0x0E 0000) 15 14 13 12 11 reserved 10 9 FCR 8 7 6 R 5 R 4 R 3 Reset value: 0000h 2 R 1 R 0 BSY1 BSY0 LOCK res. BSY3 BSY2 res.
Table 7.
Bit
Flash control register 0 low
Function Bank 3:2 Busy (XFLASH) These bits indicate that a write operation is running on the corresponding Bank of XFLASH. They are automatically set when bit WMS is set. Setting Protection operation sets bit BSY2 (since protection registers are in the Block B2). When these bits are set every read access to the corresponding Bank will output invalid data (software trap 009Bh), while every write access to the Bank will be ignored. At the end of the write operation or during a Program or Erase Suspend these bits are automatically reset and the Bank returns to read mode. After a Program or Erase Resume these bits are automatically set again.
BSY(3:2)
29/239
Internal Flash memory Table 7.
Bit
ST10F276Z5 Flash control register 0 low (continued)
Function Flash registers access locked When this bit is set, it means that the access to the Flash Control Registers FCR0H/FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read access to the registers will output invalid data (software trap 009Bh) and any write access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set. This is the only bit the user can always access to detect the status of the Flash: once it is found low, the rest of FCR0L and all the other Flash registers are accessible by the user as well. Note that FER content can be read when LOCK is low, but its content is updated only when also BSY bits are reset. Bank 1:0 Busy (IFLASH) These bits indicate that a write operation is running in the corresponding Bank of IFLASH. They are automatically set when bit WMS is set. When these bits are set every read access to the corresponding Bank will output invalid data (software trap 009Bh), while every write access to the Bank will be ignored. At the end of the write operation or during a Program or Erase Suspend these bits are automatically reset and the Bank returns to read mode. After a Program or Erase Resume these bits are automatically set again.
LOCK
BSY(1:0)
4.4.2
Flash control register 0 high
The Flash control register 0 high (FCR0H) together with the Flash control register 0 Low (FCR0L) is used to enable and to monitor all the write operations for both the Flash modules. The user has no access in write mode to the Test-Flash (B0TF). Besides, testFlash block is seen by the user in Bootstrap mode only.
FCR0H (0x0E 0002) 15
WMS
FCR 12 11
SER
Reset value: 0000h 7
SMOD
14
SUSP
13
10
9
8
SPR
6
5
4
3
Reserved
2
1
0
WPG DWPG
Reserved
RW
RW
RW
RW
RW
RW
RW
Table 8.
Bit
Flash control register 0 high
Function Select module If this bit is reset, the Write Operation is performed on XFLASH Module; if this bit is set, the Write Operation is performed on IFLASH Module. SMOD bit is automatically reset at the end of the Write operation. Set protection This bit must be set to select the Set Protection operation. The Set Protection operation allows to program 0s in place of 1s in the Flash Non Volatile Protection Registers. The Flash Address in which to program must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L before starting the execution by setting bit WMS. A sequence error is flagged by bit SEQER of FER if the address written in FARH/L is not in the range 0x0EDFB00x0EDFBF. SPR bit is automatically reset at the end of the Set Protection operation.
SMOD
SPR
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ST10F276Z5 Table 8.
Bit
Internal Flash memory Flash control register 0 high (continued)
Function Sector erase This bit must be set to select the Sector Erase operation in the Flash modules. The Sector Erase operation allows to erase all the Flash locations to 0xFF. From 1 to all the sectors of the same Bank (excluded Test-Flash for Bank B0) can be selected to be erased through bits BxFy of FCR1H/L registers before starting the execution by setting bit WMS. It is not necessary to pre-program the sectors to 0x00, because this is done automatically. SER bit is automatically reset at the end of the Sector Erase operation. Double word program This bit must be set to select the Double Word (64 bits) Program operation in the Flash modules. The Double Word Program operation allows to program 0s in place of 1s. The Flash Address in which to program (aligned with even words) must be written in the FARH/L registers, while the 2 Flash Data to be programmed must be written in the FDR0H/L registers (even word) and FDR1H/L registers (odd word) before starting the execution by setting bit WMS. DWPG bit is automatically reset at the end of the Double Word Program operation. Word program This bit must be set to select the Word (32 bits) Program operation in the Flash modules. The Word Program operation allows to program 0s in place of 1s. The Flash Address to be programmed must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L registers before starting the execution by setting bit WMS. WPG bit is automatically reset at the end of the Word Program operation. Suspend This bit must be set to suspend the current Program (Word or Double Word) or Sector Erase operation in order to read data in one of the Sectors of the Bank under modification or to program data in another Bank. The Suspend operation resets the Flash Bank to normal read mode (automatically resetting bits BSYx). When in Program Suspend, the two Flash modules accept only the following operations: Read and Program Resume. When in Erase Suspend the modules accept only the following operations: Read, Erase Resume and Program (Word or Double Word; Program operations cannot be suspended during Erase Suspend). To resume the suspended operation, the WMS bit must be set again, together with the selection bit corresponding to the operation to resume (WPG, DWPG, SER). Note: It is forbidden to start a new Write operation with bit SUSP already set. Write mode start This bit must be set to start every write operation in the Flash modules. At the end of the write operation or during a Suspend, this bit is automatically reset. To resume a suspended operation, this bit must be set again. It is forbidden to set this bit if bit ERR of FER is high (the operation is not accepted). It is also forbidden to start a new write (program or erase) operation (by setting WMS high) when bit SUSP of FCR0 is high. Resetting this bit by software has no effect.
SER
DWPG
WPG
SUSP
WMS
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Internal Flash memory
ST10F276Z5
4.4.3
Flash control register 1 low
The Flash control register 1 low (FCR1L), together with Flash control register 1 high (FCR1H), is used to select the sectors to erase, or during any write operation to monitor the status of each sector of the module selected by SMOD bit of FCR0H. First diagram shows FCR1L meaning when SMOD=0; the second one when SMOD=1.
FCR1L (0x0E 0004) SMOD=0 15 14 13 12 11 10 9 Reserved FCR 8 7 6 5 4 3 Reset value: 0000h 2 1 0
B2F2 B2F1 B2F0 RS RS RS
FCR1L (0x0E 0004) SMOD=1 15 14 13 12 11 10 9
FCR 8 7 6 5 4 3
Reset value: 0000h 2 1 0
Reserved
B0F9 B0F8 B0F7 B0F6 B0F5 B0F4 B0F3 B0F2 B0F1 B0F0 RS RS RS RS RS RS RS RS RS RS
Table 9.
Bit
Flash control register 1 low
Function
SMOD=0 (XFLASH selected) Bank 2 XFLASH sector 2:0 status These bits must be set during a Sector Erase operation to select the sectors to erase in bank 2. Besides, during any erase operation, these bits are automatically set and give the status of the 3 sectors of bank 2 (B2F2-B2F0). The meaning of B2Fy bit for sector y of bank 2 is given by the next Table 11. These bits are automatically reset at the end of a write operation if no errors are detected.
B2F(2:0)
SMOD=1 (IFLASH selected) Bank 0 IFLASH sector 9:0 status These bits must be set during a Sector Erase operation to select the sectors to erase in bank 0. Besides, during any erase operation, these bits are automatically set and give the status of the 10 sectors of bank 0 (B0F9-B0F0). The meaning of B0Fy bit for sector y of bank 0 is given by the next Table 11. These bits are automatically reset at the end of a Write operation if no errors are detected.
B0F(9:0)
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ST10F276Z5
Internal Flash memory
4.4.4
Flash control register 1 high
The Flash control register 1 high (FCR1H), together with Flash control register 1 low (FCR1L), is used to select the sectors to erase, or during any write operation to monitor the status of each sector and each bank of the module selected by SMOD bit of FCR0H. First diagram shows FCR1H meaning when SMOD=0; the second one when SMOD=1.
FCR1H (0x0E 0006) SMOD=0 15 14 13 12 11 10 9 FCR 8 7 6 5 4 3 Reset value: 0000h 2 1 0
reserved
B3S B2S RS RS FCR 10 9 8 7 6
reserved
B3F1 B3F0 RS RS
FCR1H (0x0E 0006) SMOD=1 15 14 13 12 11
Reset value: 0000h 5 4 3 2 1 0
reserved -
B1S B0S RS RS
reserved
B1F1 B1F0 RS RS
Table 10.
Bit
Flash control register 1 high
Function
SMOD=0 (XFLASH selected) Bank 3 XFLASH sector 1:0 status During any erase operation, these bits are automatically set and give the status of the 2 sectors of bank 3 (B3F1-B3F0). The meaning of B3Fy bit for sector y of bank 1 is given by the next Table 11. These bits are automatically reset at the end of a erase operation if no errors are detected. Bank 3-2 status (XFLASH) During any erase operation, these bits are automatically modified and give the status of the 2 Banks (B3-B2). The meaning of BxS bit for bank x is given in the next Table 11. These bits are automatically reset at the end of a erase operation if no errors are detected.
B3F(1:0)
B(3:2)S
SMOD=1 (IFLASH selected) Bank 1 IFLASH sector 1:0 status During any erase operation, these bits are automatically set and give the status of the 2 sectors of bank 1 (B1F1-B1F0). The meaning of B1Fy bit for sector y of bank 1 is given by the next Table 11. These bits are automatically reset at the end of a erase operation if no errors are detected. Bank 1-0 status (IFLASH) During any erase operation, these bits are automatically modified and give the status of the 2 banks (B1-B0). The meaning of BxS bit for bank x is given in the next Table 11. These bits are automatically reset at the end of a erase operation if no errors are detected.
B1F(1:0)
B(1:0)S
During any erase operation, these bits are automatically set and give the status of the 2 sectors of Bank 1 (B1F1-B1F0). The meaning of B1Fy bit for sector y of bank 1 is given by the next Table 11. These bits are automatically reset at the end of a erase operation if no errors are detected.
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Internal Flash memory Table 11.
ERR 1 0 0
ST10F276Z5 Banks (BxS) and sectors (BxFy) status bits meaning
SUSP 1 0 BxS = 1 meaning Erase error in bank x Erase suspended in bank x Don't care BxFy = 1 meaning Erase error in sector y of bank x Erase suspended in sector y of bank x Don't care
4.4.5
Flash data register 0 low
The Flash address registers (FARH/L) and the Flash data registers (FDR1H/L-FDR0H/L) are used during the program operations to store Flash Address in which to program and data to program.
FDR0L (0x0E 0008) 15 14 13 12 11 10 9
DIN9
FCR 8
DIN8
Reset value: FFFFh 7
DIN7
6
DIN6
5
DIN5
4
DIN4
3
DIN3
2
DIN2
1
DIN1
0
DIN0
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 12.
Bit
Flash data register 0 low
Function Data input 15:0 These bits must be written with the data to program the Flash with the following operations: word program (32-bit), double word program (64-bit) and set protection.
DIN(15:0)
4.4.6
Flash data register 0 high
FDR0H (0x0E 000A) 15 14 13 12 11 10 9 FCR 8 7 6 5 4 3 Reset value: FFFFh 2 1 0
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 13.
Bit
Flash data register 0 high
Function Data input 31:16 These bits must be written with the data to program the Flash with the following operations: word program (32-bit), double word program (64-bit) and set protection.
DIN(31:16)
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ST10F276Z5
Internal Flash memory
4.4.7
Flash data register 1 low
FDR1L (0x0E 000C) 15 14 13 12 11 10 9
DIN9
FCR 8
DIN8
Reset value: FFFFh 7
DIN7
6
DIN6
5
DIN5
4
DIN4
3
DIN3
2
DIN2
1
DIN1
0
DIN0
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 14.
Bit
Flash data register 1 low
Function Data Input 15:0 These bits must be written with the Data to program the Flash with the following operations: Word Program (32-bit), Double Word Program (64-bit) and Set Protection.
DIN(15:0)
4.4.8
Flash data register 1 high
FDR1H (0x0E 000E) 15 14 13 12 11 10 9 FCR 8 7 6 5 4 3 Reset value: FFFFh 2 1 0
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 15.
Bit
Flash data register 1 high
Function Data input 31:16 These bits must be written with the data to program the Flash with the following operations: word program (32-bit), double word program (64-bit) and set protection.
DIN(31:16)
4.4.9
Flash address register low
FARL (0x0E 0010) 15 14 13 12 11 10 9 FCR 8 7 6 5 4 3 Reset value: 0000h 2 1 0
ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2
reserved
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 16.
Bit
Flash address register low
Function Address 15:2 These bits must be written with the address of the Flash location to program in the following operations: word program (32-bit) and double word program (64-bit). In double word program bit ADD2 must be written to `0'.
ADD(15:2)
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ST10F276Z5
4.4.10
Flash address register high
FARH (0x0E 0012) 15 14 13 12 11 10
reserved
FCR 9 8 7 6 5 4 3
Reset value: 0000h 2 1 0
ADD20 ADD19 ADD18 ADD17 ADD16
RW
RW
RW
RW
RW
Table 17.
Bit
Flash address register high
Function
Address 20:16 ADD(20:16) These bits must be written with the address of the Flash location to program in the following operations: word program and double word program.
4.4.11
Flash error register
Flash error register, as well as all the other Flash registers, can be properly read only once LOCK bit of register FCR0L is low. Nevertheless, its content is updated when also BSY bits are reset as well; for this reason, it is definitively meaningful reading FER register content only when LOCK bit and all BSY bits are cleared.
FER (0xE 0014h) 15 14 13 12
reserved
FCR 11 10 9 8 7 6 5 4 3
Reset value: 0000h 2 1 0
ERR
WPF RESER SEQER
reserved
10ER PGER ERER
RC
RC
RC
RC
RC
RC
RC
Table 18.
Bit
Flash error register
Function Write error This bit is automatically set when an error occurs during a Flash write operation or when a bad write operation setup is done. Once the error has been discovered and understood, ERR bit must be software reset. Erase error This bit is automatically set when an erase error occurs during a Flash write operation. This error is due to a real failure of a Flash cell, that can no more be erased. This kind of error is fatal and the sector where it occurred must be discarded. This bit has to be software reset. Program error This bit is automatically set when a program error occurs during a Flash write operation. This error is due to a real failure of a Flash cell, that can no more be programmed. The word where this error occurred must be discarded. This bit has to be software reset. 1 over 0 error This bit is automatically set when trying to program at 1 bits previously set at 0 (this does not happen when programming the protection bits). This error is not due to a failure of the Flash cell, but only flags that the desired data has not been written. This bit has to be software reset.
ERR
ERER
PGER
10ER
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ST10F276Z5 Table 18.
Bit
Internal Flash memory Flash error register (continued)
Function Sequence error This bit is automatically set when the control registers (FCR1H/L-FCR0H/L, FARH/L, FDR1H/L-FDR0H/L) are not correctly filled to execute a valid write operation. in this case no write operation is executed. This bit has to be software reset. Resume error This bit is automatically set when a suspended program or erase operation is not resumed correctly due to a protocol error. In this case the suspended operation is aborted. This bit has to be software reset. Write protection flag This bit is automatically set when trying to program or erase in a sector write protected. In case of multiple sector erase, the not protected sectors are erased, while the protected sectors are not erased and bit WPF is set. This bit has to be software reset.
SEQER
RESER
WPF
4.4.12
XFlash interface control register
This register is used to configure the XFLASH interface behavior on the XBUS. It allows to set the number of wait states introduced on the XBUS before the internal READY signal is given to the ST10 bus master.
XFICR (0xE E000h) 15 14 13 12 11 10 9 XBUS 8 7 6 5 4 3
WS3
Reset value: 000Fh 2
WS2
1
WS1
0
WS0
reserved
RW
RW
RW
RW
Table 19.
Bit
XFlash interface control register
Function Wait state setting These three bits are the binary coding of the number of wait states introduced by the XFLASH interface through the XBUS internal READY signal. Default value after reset is 1111, that is the up to 15 wait states are set. The following recommendations for the ST10F276Z5 are hereafter reported: For fCPU > 40 MHz1 Wait-StateWS(3:0) = `0001' For fCPU 40 MHz0 Wait-StateWS(3:0) = `0000'
WS(3:0)
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Internal Flash memory
ST10F276Z5
4.5
Protection strategy
The protection bits are stored in Non Volatile Flash cells inside XFLASH module, that are read once at reset and stored in 7 Volatile registers. Before they are read from the Non Volatile cells, all the available protections are forced active during reset. The protections can be programmed using the Set Protection operation (see Flash Control Registers paragraph), that can be executed from all the internal or external memories except from the Flash Bank B2. Two kind of protections are available: write protections to avoid unwanted writings and access protections to avoid piracy. In next paragraphs all different level of protections are shown, and architecture limitations are highlighted as well.
4.5.1
Protection registers
The 7 Non Volatile Protection Registers are one time programmable for the user. Four registers (FNVWPXRL/H-FNVWPIRL/H) are used to store the Write Protection fuses respectively for each sector of the XFLASH Module (see X) and IFLASH module (see I). The other three Registers (FNVAPR0 and FNVAPR1L/H) are used to store the Access Protection fuses (common to both Flash modules even though with some limitations).
4.5.2
Flash non volatile write protection X register low
FNVWPXRL (0x0E DFB0) 15
W2PPR
NVR 11 10 9 8 7 6 5 4
Delivery value: FFFFh 3 2 1 0
14
13
12
reserved
W2P2W2P1W2P0 RW RW RW
RW
Table 20.
Bit
Flash non volatile write protection X register low
Function Write Protection Bank 2 sectors 2-0 (XFLASH) These bits, if programmed at 0, disable any write access to the sectors of Bank 2 (XFLASH). Write Protection Bank 2 Non Volatile cells This bit, if programmed at 0, disables any write access to the Non Volatile cells of Bank 2. Since these Non Volatile cells are dedicated to Protection registers, once W2PPR bit is set, the configuration of protection setting is frozen, and can only be modified executing a Temporary Write Unprotection operation.
W2P(2:0)
W2PPR
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ST10F276Z5
Internal Flash memory
4.5.3
Flash non volatile write protection X register high
FNVWPXRH (0x0E DF B2) 15 14 13 12 11 10 9 NVR 8 7 6 5 4 Delivery value: FFFFh 3 2 1 0
reserved
W3P1W3P0 RW RW
Table 21.
Bit
Flash non volatile write protection X register high
Function Write Protection Bank 3 / Sectors 1-0 (XFLASH) These bits, if programmed at 0, disable any write access to the sectors of Bank 3 (XFLASH).
W3P(1:0)
4.5.4
Flash non volatile write protection I register low
FNVWPIRL (0x0E DFB4) 15 14 13 12 11 10 9 NVR 8 7 6 5 4 Delivery value: FFFFh 3 2 1 0
reserved
W0P9W0P8W0P7W0P6W0P5W0P4W0P3W0P2W0P1W0P0 RW RW RW RW RW RW RW RW RW RW
Table 22.
Bit
Flash non volatile write protection I register low
Function Write Protection Bank 0 / Sectors 9-0 (IFLASH) These bits, if programmed at 0, disable any write access to the sectors of Bank 0 (IFLASH).
W0P(9:0)
4.5.5
Flash non volatile write protection I register high
FNVWPIRH (0x0E DFB6) 15 14 13 12 11 10 9 NVR 8 7 6 5 4 Delivery value: FFFFh 3 2 1 0
reserved
W1P1W1P0 RW RW
Table 23.
Bit
Flash non volatile write protection I register high
Function Write Protection Bank 1 / Sectors 1-0 (IFLASH) These bits, if programmed at 0, disable any write access to the sectors of Bank 1 (IFLASH).
W1P(1:0)
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Internal Flash memory
ST10F276Z5
4.5.6
Flash non volatile access protection register 0
Due to ST10 architecture, the XFLASH is seen as external memory: this made impossible to access protect it from real external memory or internal RAM.
FNVAPR0 (0x0E DFB8) 15 14 13 12 11 10 9 NVR 8 7 6 5 4 Delivery value: ACFFh 3 2 1
DBGP
0 ACCP RW
reserved
RW
Table 24.
Bit
Flash non volatile access protection register 0
Function Access Protection This bit, if programmed at 0, disables any access (read/write) to data mapped inside IFlash Module address space, unless the current instruction is fetched from one of the two Flash modules. Debug Protection This bit, if erased at 1, allows to by-pass all the protections using the Debug features through the Test Interface. If programmed at 0, on the contrary, all the debug features, the Test Interface and all the Flash Test modes are disabled. Even STMicroelectronics will not be able to access the device to run any eventual failure analysis.
ACCP
DBGP
4.5.7
Flash non volatile access protection register 1 low
FNVAPR1L (0x0E DFBC) 15 14 13 12 11 10 9 NVR 8
PDS8
Delivery value: FFFFh 7
PDS7
6
PDS6
5
PDS5
4
PDS4
3
PDS3
2
PDS2
1
PDS1
0
PDS0
PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 25.
Bit
Flash non volatile access protection register 1 low
Function Protections Disable 15-0 If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP is disabled. Bit PDS0 can be programmed at 0 only if bits DBGP and ACCP have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit PENx-1 has already been programmed at 0.
PDS(15:0)
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ST10F276Z5
Internal Flash memory
4.5.8
Flash non volatile access protection register 1 high
FNVAPR1H (0x0E DFBE) 15 14 13 12 11 10 9 NVR 8
PEN8
Delivery value: FFFFh 7
PEN7
6
PEN6
5
PEN5
4
PEN4
3
PEN3
2
PEN2
1
PEN1
0
PEN0
PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN9
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 26.
Bit
Flash non volatile access protection register 1 high
Function Protections Enable 15-0 If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit ACCP is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has already been programmed at 0.
PEN15-0
4.5.9
Access protection
The Flash modules have one level of access protection (access to data both in Reading and Writing): if bit ACCP of FNVAPR0 is programmed at 0, the IFlash module become access protected: data in the IFlash module can be read/written only if the current execution is from the IFlash module itself. Protection can be permanently disabled by programming bit PDS0 of FNVAPR1H, in order to analyze rejects. Allowing PDS0 bit programming only when ACCP bit is programmed, guarantees that only an execution from the Flash itself can disable the protections. Protection can be permanently enabled again by programming bit PEN0 of FNVAPR1L. The action to disable and enable again Access Protections in a permanent way can be executed a maximum of 16 times. Trying to write into the access protected Flash from internal RAM will be unsuccessful. Trying to read into the access protected Flash from internal RAM will output a dummy data. When the Flash module is protected in access, also the data access through PEC of a peripheral is forbidden. To read/write data in PEC mode from/to a protected Bank, first it is necessary to temporary unprotect the Flash module. Due to ST10 architecture, the XFLASH is seen as external memory: this makes impossible to access protect it from real external memory or internal RAM. In the following table a summary of all levels of possible Access protection is reported: in particular, supposing to enable all possible access protections, when fetching from a memory as listed in the first column, what is possible and what is not possible to do (see column headers) is shown in the table. Table 27. Summary of access protection level
Read IFLASH / Jump to IFLASH Fetching from IFLASH Fetching from XFLASH Fetching from IRAM Yes / Yes No / Yes No / Yes Read XFLASH /Jump to XFLASH Yes / Yes Yes / Yes Yes / Yes Read FLASH Registers Yes Yes Yes Write FLASH Registers Yes No No
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Internal Flash memory Table 27. Summary of access protection level (continued)
Read IFLASH / Jump to IFLASH Fetching from XRAM Fetching from External Memory No / Yes No / Yes Read XFLASH /Jump to XFLASH Yes / Yes Yes / Yes Read FLASH Registers Yes Yes
ST10F276Z5
Write FLASH Registers No No
4.5.10
Write protection
The Flash modules have one level of Write Protections: each Sector of each Bank of each Flash Module can be Software Write Protected by programming at 0 the related bit WyPx of FNVWPXRH/L-FNVWPIRH/L registers.
4.5.11
Temporary unprotection
Bits WyPx of FNVWPXRH/L-FNVWPIRH/L can be temporary unprotected by executing the Set Protection operation and writing 1 into these bits. Bit ACCP can be temporary unprotected by executing the Set Protection operation and writing 1 into these bits, but only if these write instructions are executed from the Flash Modules. To restore the write and access protection bits it is necessary to reset the microcontroller or to execute a Set Protection operation and write 0 into the desired bits. It is not necessary to temporary unprotect an access protected Flash in order to update the code: it is, in fact, sufficient to execute the updating instructions from another Flash Bank. In reality, when a temporary unprotection operation is executed, the corresponding volatile register is written to 1, while the non volatile registers bits previously written to 0 (for a protection set operation), will continue to maintain the 0. For this reason, the User software must be in charge to track the current protection status (for instance using a specific RAM area), it is not possible to deduce it by reading the non volatile register content (a temporary unprotection cannot be detected).
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ST10F276Z5
Internal Flash memory
4.6
Write operation examples
In the following, examples for each kind of Flash write operation are presented.
Word program
Example: 32-bit Word Program of data 0xAAAAAAAA at address 0x0C5554 in XFLASH Module. FCR0H|= 0x2000; /*Set WPG in FCR0H*/ FARL = 0x5554; /*Load Add in FARL*/ FARH = 0x000C; /*Load Add in FARH*/ FDR0L = 0xAAAA; /*Load Data in FDR0L*/ FDR0H = 0xAAAA; /*Load Data in FDR0H*/ FCR0H|= 0x8000; /*Operation start*/
Double word program
Example: Double Word Program (64-bit) of data 0x55AA55AA at address 0x095558 and data 0xAA55AA55 at address 0x09555C in IFLASH Module. FCR0H|= FARL = FARH = FDR0L = FDR0H = FDR1L = FDR1H = FCR0H|= 0x1080; 0x5558; 0x0009; 0x55AA; 0x55AA; 0xAA55; 0xAA55; 0x8000; /*Set DWPG, SMOD*/ /*Load Add in FARL*/ /*Load Add in FARH*/ /*Load Data in FDR0L*/ /*Load Data in FDR0H*/ /*Load Data in FDR1L*/ /*Load Data in FDR1H*/ /*Operation start*/
Double Word Program is always performed on the Double Word aligned on a even Word: bit ADD2 of FARL is ignored.
Sector erase
Example: Sector Erase of sectors B3F1 and B3F0 of Bank 3 in XFLASH Module. FCR0H|= 0x0800; /*Set SER in FCR0H*/ FCR1H|= 0x0003; /*Set B3F1, B3F0*/ FCR0H|= 0x8000; /*Operation start*/
Suspend and resume
Word Program, Double Word Program, and Sector Erase operations can be suspended in the following way: FCR0H|= 0x4000; /*Set SUSP in FCR0H*/ Then the operation can be resumed in the following way: FCR0H|= 0x0800; /*Set SER in FCR0H*/ FCR0H|= 0x8000; /*Operation resume*/ Before resuming a suspended Erase, FCR1H/FCR1L must be read to check if the Erase is already completed (FCR1H = FCR1L = 0x0000 if Erase is complete). Original setup of Select Operation bits in FCR0H/L must be restored before the operation resume, otherwise the operation is aborted and bit RESER of FER is set.
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Internal Flash memory
ST10F276Z5
Erase suspend, program and resume
A Sector Erase operation can be suspended in order to program (Word or Double Word) another Sector. Example: Sector Erase of sector B3F1 of Bank 3 in XFLASH Module. FCR0H|= 0x0800;/*Set SER in FCR0H*/ FCR1H|= 0x0002;/*Set B3F1*/ FCR0H|= 0x8000;/*Operation start*/ Example: Sector Erase Suspend. FCR0H|= do {tmp1 = tmp2 = } while 0x4000;/*Set SUSP in FCR0H*/ /*Loop to wait for LOCK=0 and WMS=0*/ FCR0L; FCR0H; ((tmp1 && 0x0010) || (tmp2 && 0x8000));
Example: Word Program of data 0x5555AAAA at address 0x0C5554 in XFLASH module. FCR0H&= 0xBFFF;/*Rst SUSP in FCR0H*/ FCR0H|= 0x2000;/*Set WPG in FCR0H*/ FARL = 0x5554; /*Load Add in FARL*/ FARH = 0x000C; /*Load Add in FARH*/ FDR0L = 0xAAAA; /*Load Data in FDR0L*/ FDR0H = 0x5555; /*Load Data in FDR0H*/ FCR0H|= 0x8000; /*Operation start*/ Once the Program operation is finished, the Erase operation can be resumed in the following way: FCR0H|= 0x0800;/*Set SER in FCR0H*/ FCR0H|= 0x8000;/*Operation resume*/ Notice that during the Program Operation in Erase suspend, bits SER and SUSP are low. A Word or Double Word Program during Erase Suspend cannot be suspended. To summarize: - - - - A Sector Erase can be suspended by setting SUSP bit To perform a Word Program operation during Erase Suspend, firstly bits SUSP and SER must be reset, then bit WPG and WMS can be set To resume the Sector Erase operation bit SER must be set again In any case it is forbidden to start any write operation with SUSP bit already set
Set protection
Example 1: Enable Write Protection of sectors B0F3-0 of Bank 0 in IFLASH module. FCR0H|= 0x0100;/*Set SPR in FCR0H*/ FARL = 0xDFB4;/*Load Add of register FNVWPIRL in FARL*/ FARH = 0x000E;/*Load Add of register FNVWPIRL in FARH*/ FDR0L = 0xFFF0;/*Load Data in FDR0L*/ FDR0H = 0xFFFF;/*Load Data in FDR0H*/ FCR0H|= 0x8000;/*Operation start*/ Notice that bit SMOD of FCR0H must not be set, since Write Protection bits of IFLASH Module are stored in Test-Flash (XFLASH Module).
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ST10F276Z5 Example 2: Enable Access and Debug Protection.
Internal Flash memory
FCR0H|= 0x0100;/*Set SPR in FCR0H*/ FARL = 0xDFB8;/*Load Add of register FNVAPR0 in FARL*/ FARH = 0x000E;/*Load Add of register FNVAPR0 in FARH*/ FDR0L = 0xFFFC;/*Load Data in FDR0L*/ FCR0H|= 0x8000;/*Operation start*/ Example 3: Disable in a permanent way Access and Debug Protection. FCR0H|= 0x0100;/*Set SPR in FCR0H*/ FARL = 0xDFBC;/*Load Add of register FNVAPR1L in FARL*/ FARH = 0x000E;/*Load Add of register FNVAPR1L in FARH*/ FDR0L = 0xFFFE; /*Load Data in FDR0L for clearing PDS0*/ FCR0H|= 0x8000;/*Operation start*/ Example 4: Enable again in a permanent way Access and Debug Protection, after having disabled them. FCR0H|= 0x0100;/*Set SPR in FCR0H*/ FARL = 0xDFBC;/*Load Add register FNVAPR1H in FARL*/ FARH = 0x000E;/*Load Add register FNVAPR1H in FARH*/ FDR0H = 0xFFFE;/*Load Data in FDR0H for clearing PEN0*/ FCR0H|= 0x8000;/*Operation start*/ Disable and re-enable of Access and Debug Protection in a permanent way (as shown by examples 3 and 4) can be done for a maximum of 16 times.
4.7
Write operation summary
In general, each write operation is started through a sequence of 3 steps: 1. The first instruction is used to select the desired operation by setting its corresponding selection bit in the Flash Control Register 0. This instruction is also used to select in which Flash Module to apply the Write Operation (by setting/resetting bit SMOD). The second step is the definition of the Address and Data for programming or the Sectors or Banks to erase. The last instruction is used to start the write operation, by setting the start bit WMS in the FCR0.
2. 3.
Once selected, but not yet started, one operation can be canceled by resetting the operation selection bit. A summary of the available Flash Module Write Operations are shown in the following Table 28.
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Internal Flash memory Table 28. Flash write operations
Operation Word Program (32-bit) Select bit WPG Address and Data FARL/FARH FDR0L/FDR0H FARL/FARH FDR0L/FDR0H FDR1L/FDR1H FCR1L/FCR1H FDR0L/FDR0H None
ST10F276Z5
Start bit WMS
Double Word Program (64-bit) Sector Erase Set Protection Program/Erase Suspend
DWPG SER SPR SUSP
WMS WMS WMS None
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ST10F276Z5
Bootstrap loader
5
Bootstrap loader
The ST10F276Z5 features innovative boot capabilities in order to support:

User defined bootstrap (see Alternate bootstrap loader) Bootstrap via UART or bootstrap via CAN for the standard bootstrap
5.1
Selection among user-code, standard or alternate bootstrap
The selection among user-code, standard bootstrap or alternate bootstrap is made by special combinations on Port0L[5...4] during the time the reset configuration is latched from Port0. The alternate boot mode is triggered with a special combination set on Port0L[5...4]. Those signals, as other configuration signals, are latched on the rising edge of RSTIN pin. The alternate boot function is divided in two functional parts (which are independent from each other):
Part 1: Selection of reset sequence according to the Port0 configuration User mode and alternate mode signatures

Decoding of reset configuration (P0L.5 = 1, P0L.4 = 1) selects the normal mode and the user Flash to be mapped from address 00'0000h. Decoding of reset configuration (P0L.5 = 1, P0L.4 = 0) selects ST10 standard bootstrap mode (Test-Flash is active and overlaps user Flash for code fetches from address 00'0000h; user Flash is active and available for read and program). Decoding of reset configuration (P0L.5 = 0, P0L.4 = 1) activates new verifications to select which bootstrap software to execute: - - If the user mode signature in the user Flash is programmed correctly, then a software reset sequence is selected and the user code is executed; If the user mode signature is not programmed correctly but the alternate mode signature in the user Flash is programmed correctly, then the alternate boot mode is selected; If both the user and the alternate mode signatures are not programmed correctly in the user Flash, then the user key location is read again. Its value will determine the behavior of the selected bootstrap loader.
-
Part 2: Running of user selected reset sequence

Standard bootstrap loader: Jump to a predefined memory location in Test-Flash (controlled by ST) Alternate boot mode: Jump to address 09'0000h Selective bootstrap loader: Jump to a predefined location in Test-Flash (controlled by ST) and check which communication channel is selected User code: Make a software reset and jump to 00'0000h
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Bootstrap loader Table 29.
P0.5 1 1 0 0
ST10F276Z5 ST10F276Z5 boot mode selection
P0.4 1 0 1 0 ST10 decoding User mode: User Flash mapped at 00'0000h Standard bootstrap loader: User Flash mapped from 00'0000h; code fetches redirected to Test-Flash at 00'0000h Alternate boot mode: Flash mapping depends on signatures integrity check Reserved
5.2
Standard bootstrap loader
The built-in bootstrap loader of the ST10F276Z5 provides a mechanism to load the startup program, which is executed after reset, via the serial interface. In this case no external (ROM) memory or an internal ROM is required for the initialization code starting at location 00'0000H. The bootstrap loader moves code/data into the IRAM but it is also possible to transfer data via the serial interface into an external RAM using a second level loader routine. ROM memory (internal or external) is not necessary. However, it may be used to provide lookup tables or may provide "core-code", that is, a set of general purpose subroutines, such as for I/O operations, number crunching or system initialization. The Bootstrap Loader can load

The complete application software into ROMless systems, Temporary software into complete systems for testing or calibration, A programming routine for Flash devices.
The BSL mechanism may be used for standard system start-up as well as for only special occasions like system maintenance (firmware update) or end-of-line programming or testing.
5.2.1
Entering the standard bootstrap loader
As with the old ST10 bootstrap mode, the ST10F276Z5 enters BSL mode if pin P0L.4 is sampled low at the end of a hardware reset. In this case, the built-in bootstrap loader is activated independently of the selected bus mode. The bootstrap loader code is stored in a special Test-Flash; no part of the standard Flash memory area is required for this. After entering BSL mode and the respective initialization, the ST10F276Z5 scans the RxD0 line and the CAN1_RxD line to receive either a valid dominant bit from the CAN interface or a start condition from the UART line.
Start condition on UART RxD
The ST10F276Z5 starts the standard bootstrap loader. This bootstrap loader is identical to other ST10 devices (Examples: ST10F269, ST10F168). See paragraph 5.3 for details.
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Bootstrap loader
Valid dominant bit on CAN1 RxD
The ST10F276Z5 starts bootstrapping via CAN1; the bootstrapping method is new and is described in the next paragraph 5.4. Figure 5 shows the program flow of the new bootstrap loader. It clearly illustrates how the new functionalities are implemented:

UART: UART has priority over CAN after a falling edge on CAN1_RxD until the first valid rising edge on CAN1_RxD; CAN: Pulses on CAN1_RxD shorter than 20*CPU-cycles are filtered.
5.2.2
ST10 configuration in BSL
When the ST10F276Z5 has entered BSL mode, the configuration shown in Table 30 is automatically set (values that deviate from the normal reset values are marked in bold). Table 30. ST10 configuration in BSL mode
Access Disabled 0404H (1) FA00H FC00H FA40H FA00H access to startup configuration(2) 8011H access to `00' byte `1' `1' 0000H access to `0' frame 042DH `1' `1' Initialized only if Bootstrap via UART Initialized only if Bootstrap via UART Initialized only if Bootstrap via UART Initialized only if Bootstrap via UART Initialized only if Bootstrap via CAN Initialized only if Bootstrap via CAN XRAM1-2, XFlash, CAN1 and XMISC enabled. Initialized only if Bootstrap via CAN Initialized only if Bootstrap via CAN Initialized only if Bootstrap via CAN XPEN bit set for Bootstrap via CAN or Alternate Boot mode Notes
Function or register Watchdog Timer Register SYSCON Context Pointer CP Register STKUN Stack Pointer SP Register STKOV Register BUSCON0 Register S0CON Register S0BG P3.10 / TXD0 DP3.10 CAN1 Status/Control Register CAN1 Bit Timing Register XPERCON P4.6 / CAN1_TxD DP4.6
1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration. 2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.
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Bootstrap loader Figure 5. ST10F276Z5 new standard bootstrap loader program flow
START
ST10F276Z5
Falling-edge on UART0 RxD?
No
Falling-edge on CAN1 RxD?
No
UART BOOT
Start timer PT0 Start timer T6 Yes No UART0 RxD = 1?
UART RxD = 0?
Stop timer T6 Initialize UART Send acknowledge Address = FA40h
CAN1 RxD = 1?
No
PT0 > 20? No Byte received? Count = 1 [Address] = S0RBUF Address = Address + 1 CAN RxD = 0? No Address = FA60h?
No
CAN BOOT
Glitch on CAN1 RxD
Stop timer PT0 Clear timer PT0 No
CAN1 RxD = 1?
No
Message received?
No
Count += 1
[Address] = MO15_data0 Address = Address + 1 No Address = FAC0h? No
Count = 5?
Stop timer PT0 Initialize CAN Address = FA40h
UART BOOT
CAN BOOT
Jump to address FA40h
Other than after a normal reset the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Depending on the selected serial link (UART0 or CAN1), pin TxD0 or CAN1_TxD is configured as output, so the ST10F276Z5 can return the acknowledge byte. Even if the internal IFLASH is enabled, a code cannot be executed from it.
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5.2.3
Booting steps
As Figure 6 shows, booting the device with the boot loader code occurs in a minimum of four steps: 1. 2. The device is reset with P0L.4 low. The internal new bootstrap code runs on the ST10 and a first level user code is downloaded from the external device, via the selected serial link (UART0 or CAN1). The bootstrap code is contained in the device Test-Flash and is automatically run when the device is reset with P0L.4 low. After loading a preselected number of bytes, the ST10F276Z5 begins executing the downloaded program. The first level user code runs on the ST10F276Z5. Typically, this first level user code is another loader that downloads the application software into the device. The loaded application software is now running. Booting steps for ST10F276Z5
3. 4.
Figure 6.
Serial Link
Step 1 Entering bootstrap
External device
ST10F276Z5
Step 2 Loading first level user code
External device
Download First level user code
ST10F276Z5 Run bootstrap code from Test-Flash
Serial Link
Step 3 Loading the application and exiting BSL
External device
Download Application
ST10F276Z5 Run first level code from DPRAM @ FA40h
Serial Link Serial Link
ST10F276Z5 Run application code
Step 4
External device
5.2.4
Hardware to activate BSL
The hardware that activates the BSL during reset may be a simple pull-down resistor on P0L.4 for systems that use this feature at every hardware reset. For systems that use the bootstrap loader only temporarily, it may be preferable to use a switchable solution (via jumper or an external signal).
Note:
CAN alternate function on Port4 lines is not activated if the user has selected eight address segments (Port4 pins have three functions: I/O port, address segment and CAN). Boot via CAN requires that four or less address segments are selected.
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Bootstrap loader Figure 7. Hardware provisions to activate the BSL
External signal
ST10F276Z5
Normal boot P0L.4 P0L.4 BSL
RP0L.4 8k max.
RP0L.4 8k max.
Circuit 2 Circuit 1
5.2.5
Memory configuration in bootstrap loader mode
The configuration (that is, the accessibility) of the device memory areas after reset in Bootstrap Loader mode differs from the standard case. Pin EA is evaluated when BSL mode is selected to enable or to not enable the external bus:

If EA = 1, the external bus is disabled (BUSACT0 = 0 in BUSCON0 register); If EA = 0, the external bus is enabled (BUSACT0 = 1 in BUSCON0 register). All code accesses are made from the special Test-Flash seen in the range 00'0000h to 00'01FFFh; User IFLASH is only available for read and write accesses (Test-Flash cannot be read or written); Write accesses must be made with addresses starting in segment 1 from 01'0000h, regardless of the value of ROMS1 bit in SYSCON register; Read accesses are made in segment 0 or in segment 1 depending on the ROMS1 value; In BSL mode, by default, ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in segment 0.
Moreover, while in BSL mode, accesses to the internal IFLASH area are partially redirected:

Example
In default configuration, to program address 0, the user must put the value 01'0000h in the FARL and FARH registers but to verify the content of the address 0 a read to 00'0000h must be performed.
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ST10F276Z5 Figure 8. Memory configuration after reset
16 Mbytes
255
Bootstrap loader
16 Mbytes
255
16 Mbytes
255 1 int. RAM
Depends on reset config. (EA, P0)
access to external bus 1 disabled int. RAM 0
user FLASH Test-Flash
1 int. RAM 0
user FLASH
access to external bus enabled
0 access to int. FLASH enabled
user FLASH
access to int. FLASH enabled
Test-Flash
Depends on reset config.
BSL mode active EA pin Code fetch from internal FLASH area Data fetch from internal FLASH area
Yes (P0L.4 = `0') High Test-FLASH access User IFLASH access
Yes (P0L.4 = `0') Low Test-FLASH access User IFLASH access
No (P0L.4 = `1') According to application User IFLASH access User IFLASH access
1. As long as the device is in BSL, the user's software should not try to execute code from the internal IFlash, as the fetches are redirected to the Test-Flash.
5.2.6
Loading the start-up code
After the serial link initialization sequence (see following chapters), the BSL enters a loop to receive 32 bytes (boot via UART) or 128 bytes (boot via CAN). These bytes are stored sequentially into the device Dual-Port RAM from location 00'FA40h. To execute the loaded code, the BSL then jumps to location 00'FA40h. The bootstrap sequence running from the Test-Flash is now terminated; however, the microcontroller remains in BSL mode. Most probably, the initially loaded routine, being the first level user code, will load additional code and data. This first level user code may use the pre-initialized interface (UART or CAN) to receive data and a second level of code, and store it in arbitrary user-defined locations. This second level of code may be

The final application code Another, more sophisticated, loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data A code sequence to change the system configuration and enable the bus interface to store the received data into external memory
In all cases, the device still runs in BSL mode, that is, with the watchdog timer disabled and limited access to the internal IFLASH area.
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5.2.7
Exiting bootstrap loader mode
To execute a program in normal mode, the BSL mode must first be terminated. The device exits BSL mode at a software reset (level on P0L.4 is ignored) or a hardware reset (P0L.4 must be high in this case). After the reset, the device starts executing from location 00'0000H of the internal Flash (User Flash) or the external memory, as programmed via pin EA.
Note:
If a bidirectional Software Reset is executed and external memory boot is selected (EA = 0), a degeneration of the Software Reset event into a Hardware Reset can occur (refer to section for details). This implies that P0L.4 becomes transparent, so to exit from Bootstrap mode it would be necessary to release pin P0L.4 (it is no longer ignored).
5.2.8
Hardware requirements
Although the new bootstrap loader is designed to be compatible with the old bootstrap loader, there are a few hardware requirements relative to the new bootstrap loader:

External Bus configuration: Must have four or less segment address lines (keep CAN I/Os available); Usage of CAN pins (P4.5 and P4.6): Even in bootstrap via UART, P4.5 (CAN1_RxD) can be used as Port input but not as output. The pin P4.6 (CAN1_TxD) can be used as input or output. Level on UART RxD and CAN1_RxD during the bootstrap phase (see Figure 6 - Step 2): Must be 1 (external pull-ups recommended).
5.3
5.3.1
Standard bootstrap with UART (RS232 or K-Line)
Features
The device bootstrap via UART has the same overall behavior as the old ST10 bootstrap via UART:

Same bootstrapping steps; Same bootstrap method: Analyze the timing of a predefined byte, send back an acknowledge byte, load a fixed number of bytes and run; Same functionalities: Boot with different crystals and PLL ratios.
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ST10F276Z5 Figure 9.
RSTIN
Bootstrap loader UART bootstrap loader sequence
P0L.4
1) 2) 4)
RxD0
3)
TxD0
5)
CSP:IP
6)
Int. Boot ROM / Test-Flash BSL-routine 32 bytes user software
1. 2. 3. 4. 5. 6.
BSL initialization time, > 1ms @ fCPU = 40 MHz. Zero byte (1 start bit, eight `0' data bits, 1 stop bit), sent by host. Acknowledge byte, sent by the ST10F276Z5. 32 bytes of code / data, sent by host. Caution: TxD0 is only driven a certain time after reception of the zero byte (1.3ms @ fCPU = 40 MHz). Internal Boot ROM / Test-Flash.
5.3.2
Entering bootstrap via UART
The device enters BSL mode if pin P0L.4 is sampled low at the end of a hardware reset. In this case, the built-in bootstrap loader is activated independently of the selected bus mode. The bootstrap loader code is stored in a special Test-Flash; no part of the standard mask ROM or Flash memory area is required for this. After entering BSL mode and the respective initialization, the device scans the RxD0 line to receive a zero byte, that is, 1 start bit, eight `0' data bits and 1 stop bit. From the duration of this zero byte, it calculates the corresponding baud rate factor with respect to the current CPU clock, initializes the serial interface ASC0 accordingly and switches pin TxD0 to output. Using this baud rate, an acknowledge byte is returned to the host that provides the loaded data. The acknowledge byte is D5h for the ST10F276Z5.
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5.3.3
ST10 Configuration in UART BSL (RS232 or K-Line)
When the ST10F276Z5 enters BSL mode on UART, the configuration shown in Table 31 is automatically set (values that deviate from the normal reset values are marked in bold). Table 31. ST10 configuration in UART BSL mode (RS232 or K-line)
Access Disabled 0400H(1) FA00H FA00H FA40H FC00H access to startup configuration(2) 8011H access to `00' byte `1' `1' Initialized only if Bootstrap via UART Initialized only if Bootstrap via UART Initialized only if Bootstrap via UART Initialized only if Bootstrap via UART Notes
Function or register Watchdog timer Register SYSCON Context Pointer CP Register STKUN Stack Pointer SP Register STKOV Register BUSCON0 Register S0CON Register S0BG P3.10 / TXD0 DP3.10
1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration. 2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.
Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Pin TxD0 is configured as output, so the ST10F276Z5 can return the acknowledge byte. Even if the internal IFLASH is enabled, a code cannot be executed from it.
5.3.4
Loading the start-up code
After sending the acknowledge byte, the BSL enters a loop to receive 32 bytes via ASC0. These bytes are stored sequentially into locations 00'FA40H through 00'FA5FH of the IRAM, allowing up to 16 instructions to be placed into the RAM area. To execute the loaded code the BSL then jumps to location 00'FA40H, that is, the first loaded instruction. The bootstrap loading sequence is now terminated; however, the device remains in BSL mode. The initially loaded routine will most probably load additional code or data, as an average application is likely to require substantially more than 16 instructions. This second receive loop may directly use the pre-initialized interface ASC0 to receive data and store it in arbitrary userdefined locations. This second level of loaded code may be

the final application code another, more sophisticated, loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data a code sequence to change the system configuration and enable the bus interface to store the received data into external memory
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This process may go through several iterations or may directly execute the final application. In all cases the device still runs in BSL mode, that is, with the watchdog timer disabled and limited access to the internal Flash area. All code fetches from the internal IFLASH area (01'0000H...08'FFFFH) are redirected to the special Test-Flash. Data read operations access the internal Flash of the device.
5.3.5
Choosing the baud rate for the BSL via UART
The calculation of the serial baud rate for ASC0 from the length of the first zero byte that is received allows the operation of the bootstrap loader of the device with a wide range of baud rates. However, the upper and lower limits must be kept to ensure proper data transfer.
BST10F276 = f CPU --------------------------------------------32 ( S0BRL + 1 )
The device uses timer T6 to measure the length of the initial zero byte. The quantization uncertainty of this measurement implies the first deviation from the real baud rate; the next deviation is implied by the computation of the S0BRL reload value from the timer contents. The formula below shows the association:
9 f CPUT6 - 36 S0BRL = ------------------- , T6 = -- ---------------4 B Host 72
For a correct data transfer from the host to the device, the maximum deviation between the internal initialized baud rate for ASC0 and the real baud rate of the host should be below 2.5%. The deviation (FB, in percent) between host baud rate and device baud rate can be calculated using the formula below:
B Contr - B Host F B = ------------------------------------------- 100 % , B Contr F B 2.5 %
Note:
Function (FB) does not consider the tolerances of oscillators and other devices supporting the serial communication. This baud rate deviation is a nonlinear function depending on the CPU clock and the baud rate of the host. The maxima of the function (FB) increases with the host baud rate due to the smaller baud rate prescaler factors and the implied higher quantization error (see Figure 10). Figure 10. Baud rate deviation between host and ST10F276Z5
FB 2.5%
I
BLow
BHigh
II
BHOST
The minimum baud rate (BLow in Figure 10) is determined by the maximum count capacity of timer T6, when measuring the zero byte, that is, it depends on the CPU clock. Using the maximum T6 count 216 in the formula the minimum baud rate is calculated. The lowest
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standard baud rate in this case would be 1200 baud. Baud rates below BLow would cause T6 to overflow. In this case, ASC0 cannot be initialized properly. The maximum baud rate (BHigh in Figure 10) is the highest baud rate where the deviation still does not exceed the limit, that is, all baud rates between BLow and BHigh are below the deviation limit. The maximum standard baud rate that fulfills this requirement is 19200 baud. Higher baud rates, however, may be used as long as the actual deviation does not exceed the limit. A certain baud rate (marked "I" in Figure 10) may, for example, violate the deviation limit, while an even higher baud rate (marked "II" in Figure 10) stays well below it. This depends on the host interface.
5.4
5.4.1
Standard bootstrap with CAN
Features
The bootstrap via CAN has the same overall behavior as the bootstrap via UART:

Same bootstrapping steps; Same bootstrap method: Analyze the timing of a predefined frame, send back an acknowledge frame BUT only on request, load a fixed number of bytes and run; Same functionalities: Boot with different crystals and PLL ratios.
Figure 11. CAN bootstrap loader sequence
RSTIN
P0L.4
1) 2) 4)
CAN1_RxD
3)
CAN1_TxD
5)
CSP:IP
6) Int. Boot ROM / Test-Flash BSL-routine
128bytes user software
1. 2. 3. 4. 5. 6.
BSL initialization time, > 1ms @ fCPU = 40 MHz. Zero frame (CAN message: standard ID = 0, DLC = 0), sent by host. CAN message (standard ID = E6h, DLC = 3, Data0 = D5h, Data1-Data2 = IDCHIP_low-high), sent by the ST10F276Z5 on request. 128 bytes of code / data, sent by host. Caution: CAN1_TxD is only driven a certain time after reception of the zero byte (1.3ms @ fCPU = 40 MHz). Internal Boot ROM / Test-Flash.
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ST10F276Z5 The Bootstrap Loader can load

Bootstrap loader
the complete application software into ROM-less systems, temporary software into complete systems for testing or calibration, a programming routine for Flash devices.
The BSL mechanism may be used for standard system start-up as well as for only special occasions like system maintenance (firmware update) or end-of-line programming or testing.
5.4.2
Entering the CAN bootstrap loader
The ST10F276Z5 enters BSL mode if pin P0L.4 is sampled low at the end of a hardware reset. In this case, the built-in bootstrap loader is activated independently of the selected bus mode. The bootstrap loader code is stored in a special Test-Flash; no part of the standard mask ROM or Flash memory area is required for this. After entering BSL mode and the respective initialization, the device scans the CAN1_TxD line to receive the following initialization frame:

Standard identifier = 0h DLC = 0h
As all the bits to be transmitted are dominant bits, a succession of 5 dominant bits and 1 stuff bit on the CAN network is used. From the duration of this frame, it calculates the corresponding baud rate factor with respect to the current CPU clock, initializes the CAN1 interface accordingly, switches pin CAN1_TxD to output and enables the CAN1 interface to take part in the network communication. Using this baud rate, a Message Object is configured in order to send an acknowledge frame. The device does not send this Message Object but the host can request it by sending a remote frame. The acknowledge frame is the following for the ST10F276Z5:

Standard identifier = E6h DLC = 3h Data0 = D5h, that is, generic acknowledge of the ST10 devices Data1 = IDCHIP least significant byte Data2 = IDCHIP most significant byte
For the ST10F276Z5, IDCHIP is set to 114Xh. Note: Two behaviors can be distinguished in ST10 acknowledging to the host. If the host is behaving according to the CAN protocol, as at the beginning the ST10 CAN is not configured, the host is alone on the CAN network and does not receive an acknowledge. It automatically sends again the zero frame. As soon as the ST10 CAN is configured, it acknowledges the zero frame. The "acknowledge frame" with identifier 0xE6 is configured, but the Transmit Request is not set. The host can request this frame to be sent and therefore obtains the IDCHIP by sending a remote frame. Hint: As the IDCHIP is sent in the acknowledge frame, Flash programming software now can immediately identify the exact type of device to be programmed.
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5.4.3
ST10 configuration in CAN BSL
When the ST10F276Z5 enters BSL mode via CAN, the configuration shown in Table 32 is automatically set (values that deviate from the normal reset values are marked in bold). Table 32. ST10 configuration in CAN BSL
Access Disabled 0404H (1) FA00H FA00H FA40H FC00H access to startup configuration(2) Initialized only if Bootstrap via CAN Initialized only if Bootstrap via CAN XRAM1-2, XFlash, CAN1 and XMISC enabled Initialized only if Bootstrap via CAN Initialized only if Bootstrap via CAN XPEN bit set Notes
Function or register Watchdog timer Register SYSCON Context pointer CP Register STKUN Stack pointer SP Register STKOV Register BUSCON0
CAN1 Status/Control register 0000H CAN1 Bit timing register XPERCON P4.6 / CAN1_TxD DP4.6 access to `0' frame 042DH `1' `1'
1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration. 2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.
Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Pin CAN1_TxD1 is configured as output, so the ST10F276Z5 can return the identification frame. Even if the internal IFLASH is enabled, a code cannot be executed from it.
5.4.4
Loading the start-up code via CAN
After sending the acknowledge byte, the BSL enters a loop to receive 128 bytes via CAN1. Hint: The number of bytes loaded when booting via the CAN interface has been extended to 128 bytes to allow the reconfiguration of the CAN Bit Timing Register with the best timings (synchronization window, ...). This can be achieved by the following sequence of instructions: ReconfigureBaud rate: MOV R1,#041h MOV DPP3:0EF00h,R1 ; Put CAN in Init, enable Configuration Change MOV R1,#01600h MOV DPP3:0EF06h,R1 ; 1MBaud at Fcpu = 20 MHz These 128 bytes are stored sequentially into locations 00'FA40H through 00'FABFH of the IRAM, allowing up to 64 instructions to be placed into the RAM area. To execute the loaded code the BSL then jumps to location 00'FA40H, that is, the first loaded instruction. The bootstrap loading sequence is now terminated; however, the ST10F276Z5 remains in BSL
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mode. Most probably the initially loaded routine will load additional code or data, as an average application is likely to require substantially more than 64 instructions. This second receive loop may directly use the pre-initialized CAN interface to receive data and store it in arbitrary user-defined locations. This second level of loaded code may be

the final application code another, more sophisticated, loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data a code sequence to change the system configuration and enable the bus interface to store the received data into external memory
This process may go through several iterations or may directly execute the final application. In all cases the ST10F276Z5 still runs in BSL mode, that is, with the watchdog timer disabled and limited access to the internal Flash area. All code fetches from the internal Flash area (01'0000H ...08'FFFFH) are redirected to the special Test-Flash. Data read operations will access the internal Flash of the ST10F276Z5.
5.4.5
Choosing the baud rate for the BSL via CAN
The Bootstrap via CAN acts the same way as in the UART bootstrap mode. When the ST10F276Z5 is started in BSL mode, it polls the RxD0 and CAN1_RxD lines. When polling a low level on one of these lines, a timer is launched that is stopped when the line returns to high level. For CAN communication, the algorithm is made to receive a zero frame, that is, the standard identifier is 0x0, DLC is 0. This frame produces the following levels on the network: 5D, 1R, 5D, 1R, 5D, 1R, 5D, 1R, 5D, 1R, 4D, 1R, 1D, 11R. The algorithm lets the timer run until the detection of the 5th recessive bit. This way the bit timing is calculated over the duration of 29 bit times: This minimizes the error introduced by the polling. Figure 12. Bit rate measurement over a predefined zero-frame
Start Stuff bit Stuff bit Stuff bit Stuff bit ........
Measured time
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Bootstrap loader Error induced by the polling The code used for the polling is the following: WaitCom: JNB P4.5,CAN_Boot CAN JB P3.11,WaitCom BSET T6R .... CAN_Boot: BSET PWMCON0.0
ST10F276Z5
; if SOF detected on CAN, then go to ; loader ; Wait for start bit at RxD0 ; Start Timer T6
; Start PWM Timer0 ; (resolution is 1 CPU clk cycle) JMPR cc_UC,WaitRecessiveBit WaitDominantBit: JB P4.5,WaitDominantBit; wait for end of stuff bit WaitRecessiveBit: JNB P4.5,WaitRecessiveBit; wait for 1st dominant bit = Stuff bit CMPI1R1,#5 ; Test if 5th stuff bit detected JMPR cc_NE,WaitDominantBit; No, go back to count more BCLR PWMCON.0 ; Stop timer ; here the 5th stuff bit is detected: ; PT0 = 29 Bit_Time (25D and 4R) Therefore the maximum error at the detection of the communication on CAN pin is: (1 not taken + 1 taken jumps) + 1 taken jump + 1 bit set: (6) + 6 CPU clock cycles The error at the detection for the 5th recessive bit is: (1 taken jump) + 1 not taken jump + 1 compare + 1 bit clear: (4) + 6 CPU cycles In the worst case, the induced error is 6 CPU clock cycles, so the polling could induce an error of 6 timer ticks. Error induced by the baud rate calculation The content of the timer PT0 counter corresponds to 29 bit times, resulting in the following equation: PT0 = 58 x (BRP + 1) X (1 + Tseg1 + Tseg2) where BRP, Tseg1 and Tseg2 are the field of the CAN Bit Timing register. The CAN protocol specification recommends to implement a bit time composed of at least 8 time quanta (tq). This recommendation is applied here. Moreover, the maximum bit time length is 25 tq. To ensure precision, the aim is to have the smallest Bit Rate Prescaler (BRP) and the maximum number of tq in a bit time. This gives the following ranges for PT0 according to BRP: 8 1 + Tseg1 + Tseg2 25 464 x (1 + BRP) PT0 1450 x (1 + BRP)
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ST10F276Z5 Table 33. BRP and PT0 values
PT0_min 464 1451 2901 4351 5801 7251 .. 20416 20880 21344 .. X PT0_max 1450 2900 4350 5800 7250 8700 .. 63800 65250 66700 .. X
Bootstrap loader
BRP 0 1 2 3 4 5 .. 43 44 45 .. 63
Comments
Possible timer overflow
The error coming from the measurement of the 29 bit is: e1 = 6 / [PT0] It is maximal for the smallest BRP value and the smallest number of ticks in PT0. Therefore: e1 Max = 1.29% To improve precision, the aim is to have the smallest BRP so that the time quantum is the smallest possible. Thus, an error on the calculation of time quanta in a bit time is minimal. In order to do so, the value of PT0 is divided into ranges of 1450 ticks. In the algorithm, PT0 is divided by 1451 and the result is BRP. The calculated BRP value is then used to divide PT0 in order to have the value of (1 + Tseg1 + Tseg2). A table is made to set the values for Tseg1 and Tseg2 according to the value of (1 + Tseg1 + Tseg2). These values of Tseg1 and Tseg2 are chosen in order to reach a sample point between 70% and 80% of the bit time. During the calculation of (1 + Tseg1 + Tseg2), an error e2 can be introduced by the division. This error is of 1 time quantum maximum. To compensate for any possible error on bit rate, the (Re)Synchronization Jump Width is fixed to 2 time quanta.
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5.4.6
Computing the baud rate error
Considering the following conditions, a computation of the error is given as an example.

CPU frequency: 20 MHz Target Bit Rate: 1 Mbit/s 29 x Fcpu [ PT0 ] = -------------------------- = 29 x 20 x 6 = 580 - ---------------------------BitRate 6 1 x 10
In these conditions, the content of PT0 timer for 29 bits should be:
Therefore: 574 < [PT0] < 586 This gives: BRP = 0 tq = 100 ns Computation of 1 + Tseg1 + Tseg2: Considering the equation: [PT0] = 58 x (1 + BRP) x (1 + Tseg1 + Tseg2) Thus: 574 586 9 = --------- Tseg1 + Tseg2 --------- = 10 58 58 In the algorithm, a rounding up to the superior value is made if the remainder of the division is greater than half of the divisor. This would have been the case if the PT0 content was 574. Thus, in this example the result is 1 + Tseg1 + Tseg2 = 10, giving a bit time of exactly 1s => no error in bit rate. Note: In most cases (24 MHz, 32 MHz, 40 MHz of CPU frequency and 125, 250, 500 or 1Mb/s of bit rate), there is no error. Nevertheless, it is better to check for an error with the real application parameters. The content of the bit timing register is: 0x1640. This gives a sample point at 80%. Note: The (Re)Synchronization Jump Width is fixed to 2 time quanta.
5.4.7
Bootstrap via CAN
After the bootstrap phase, the ST10F276Z5 CAN module is configured as follows:

The pin P4.6 is configured as output (the latch value is `1' = recessive) to assume CAN1_TxD function. The MO2 is configured to output the acknowledge of the bootstrap with the standard identifier E6h, a DLC of 3 and Data0 = D5h, Data1 and 2 = IDCHIP. The MO1 is configured to receive messages with the standard identifier 5h. Its acceptance mask is set to ensure that all bits match. The DLC received is not checked: The ST10 expects only 1 byte of data at a time.
No other message is sent by the ST10F276Z5 after the acknowledge. Note: The CAN boot waits for 128 bytes of data instead of 32 bytes (see UART boot). This is done to allow the User to reconfigure the CAN bit rate as soon as possible.
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ST10F276Z5
Bootstrap loader
5.5
Comparing the old and the new bootstrap loader
The following tables summarizes the differences between the old ST10 (boot via UART only) bootstrap and the new one (boot via UART or CAN). Table 34. Software topics summary
New bootstrap loader Comments For compatibility between boot via UART and boot via CAN1, please avoid loading the application software in the 00'FA60h/00'FABFh range. Same files can be used for boot via UART. User can change the Xperipherals selections through a specific code.
Old bootstrap loader
Uses up to 128 bytes in Uses only 32 bytes in DualDual-Port RAM from Port RAM from 00'FA40h 00'FA40h Loads 32 bytes from UART Loads 32 bytes from UART (boot via UART mode)
User selected Xperipherals Xperipherals selection is can be enabled during boot fixed. (Step 3 or Step 4).
5.5.1
Software aspects
As the CAN1 is needed, XPERCON register is configured by the bootstrap loader code and bit XPEN of SYSCON is set. However, as long as the EINIT instruction is not executed (and it is not in the bootstrap loader code), the settings can be modified. To do this, perform the following steps:

DIsable the XPeripherals by clearing XPEN in SYSCON register. Attention: If this part of the code is located in XRAM, it will be disabled. Enable the needed XPeripherals by writing the correct value in XPERCON register. Set XPEN bit in SYSCON.
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5.5.2
Hardware aspects
Although the new bootstrap loader is designed to be compatible with the old bootstrap loader, there are a few hardware requirements for the new bootstrap loader as summarized in Table 35. Table 35. Hardware topics summary
New bootstrap loader P4.5 cannot be used as user output in BSL mode, but only as CAN1_RxD or input or address segments. Level on CAN1_RxD must be stable at `1' during boot Step 2. External pull-up on P4.5 needed. Comments
Actual bootstrap loader P4.5 can be used as output in BSL mode. Level on CAN1_RxD can change during boot Step 2.
5.6
5.6.1
Alternate boot mode (ABM)
Activation
Alternate boot is activated with the combination `01' on Port0L[5..4] at the rising edge of RSTIN.
5.6.2
Memory mapping
The ST10F276Z5 has the same memory mapping for standard boot mode and for alternate boot mode:

Test-Flash: Mapped from 00'0000h. The Standard Bootstrap Loader can be started by executing a jump to the address of this routine (JMPS 00'xxxx; address to be defined). User Flash: The User Flash is divided in two parts: The IFLASH, visible only for memory reads and memory writes (no code fetch) and the XFLASH, visible for any ST10 access (memory read, memory write and code fetch). All device XRAM and Xperipherals modules can be accessed if enabled in XPERCON register.
Note:
The alternate boot mode can be used to reprogram the whole content of the device User Flash (except Block 0 in Bank 2, where the alternate boot is mapped into).
5.6.3
Interrupts
The ST10 interrupt vector table is always mapped from address 00'0000h. As a consequence, interrupts are not allowed in Alternate Boot mode; all maskable and non maskable interrupts must be disabled.
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ST10F276Z5
Bootstrap loader
5.6.4
ST10 configuration in alternate boot mode
When the ST10F276Z5 enters BSL mode via CAN, the configuration shown in Table 36 is automatically set (values that deviate from the normal reset values are marked in bold). Table 36. ST10 configuration in alternate boot mode
Access Disabled 0404H(1) FA00H FA00H FA40H FC00H access to startup configuration(2) 002DH XRAM1-2, XFlash, CAN1 enabled XPEN bit set Notes
Function or register Watchdog timer Register SYSCON Context pointer CP Register STKUN Stack pointer SP Register STKOV Register BUSCON0 XPERCON
1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration. 2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.
Even if the internal IFLASH is enabled, a code cannot be executed from it. As the XFlash is needed, XPERCON register is configured by the ABM loader code and bit XPEN of SYSCON is set. However, as long as the EINIT instruction is not executed (and it is not in the bootstrap loader code), the settings can be modified. To do this, perform the following steps:
Copy in DPRAM a function that will - - - - disable the XPeripherals by clearing XPEN in SYSCON register, enabled the needed XPeripherals by writing the correct value in XPERCON register, set XPEN bit in SYSCON, return to calling address.
Call the function from XFlash
The changing of the XPERCON value cannot be executed from the XFlash because the XFlash is disabled by the clearing of XPEN bit in SYSCON.
5.6.5
Watchdog
As for standard boot, the Watchdog timer remains disabled during Alternate Boot mode. In case a Watchdog reset occurs, a software reset is generated.
Note:
See note from Section 5.2.7 concerning software reset.
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5.6.6
Note:
Exiting alternate boot mode
Once the ABM mode is entered, it can be exited only with a software or hardware reset. See note from Section 5.2.7 concerning software reset.
5.6.7
Alternate boot user software
If the rules described previously are respected (that is, mapping of variables, disabling of interrupts, exit conditions, predefined vectors in Block 0 of Bank 2, Watchdog usage), then users can write the software they want to execute in this mode starting from 09'0000h.
5.6.8
User/alternate mode signature integrity check
The behavior of the Alternate Boot mode is based on the computing of a signature between the content of two memory locations and a comparison with a reference signature. This requires that users who use Alternate Boot have reserved and programmed the Flash memory locations according to: User mode signature 00'0000h: memory address of operand0 for the signature computing 00'1FFCh: memory address of operand1 for the signature computing 00'1FFEh: memory address for the signature reference Alternate mode signature 09'0000h: memory address of operand0 for the signature computing 09'1FFCh: memory address of operand1 for the signature computing 09'1FFEh: memory address for the signature reference The values for operand0, operand1 and the signature should be such that the sequence shown in the figure below is successfully executed. MOV ADD CPLB CMP Rx, CheckBlock1Addr; 00'0000h for standard reset Rx, CheckBlock2Addr; 00'1FFCh for standard reset RLx ; 1s complement of the lower ; byte of the sum Rx, CheckBlock3Addr; 00'1FFEh for standard reset
5.6.9
Alternate boot user software aspects
User defined alternate boot code must start at 09'0000h. A new SFR created on the ST10F276Z5 indicates that the device is running in Alternate Boot mode: Bit 5 of EMUCON (mapped at 0xFE0Ah) is set when the alternate boot is selected by the reset configuration. All the other bits are ignored when checking the content of this register to read the value of bit 5. This bit is a read-only bit. It remains set until the next software or hardware reset.
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ST10F276Z5
Bootstrap loader
5.6.10
EMUCON register
EMUCON (FE0Ah / 05h) 15 14 13 12 11 10 9 SFR 8 7 6 5 ABM R 4 3 Reset value: - xxh: 2 1 0
Table 37.
Bit
ABM bit description
Function ABM Flag (or TMOD3) `0': Alternate Boot mode is not selected by reset configuration on P0L[5..4] `1': Alternate Boot mode is selected by reset configuration on P0L[5..4]: This bit is set if P0L[5..4] = `01' during hardware reset.
ABM
5.6.11
Internal decoding of test modes
The test mode decoding logic is located inside the ST10F276Z5 Bus Controller. The decoding is as follows:

Alternate Boot mode decoding: (P0L.5 & P0L.4) Standard Bootstrap decoding: (P0L.5 & P0L.4) Normal operation: (P0L.5 & P0L.4)
The other configurations select ST internal test modes.
5.6.12
Example
In the following example, Alternate Boot mode works as follows: on rising edge of RSTIN pin, the reset configuration is latched:

If Bootstrap Loader mode is not enabled (P0L[5..4] = `11'), the device hardware proceeds with a standard hardware reset procedure. If standard Bootstrap Loader is enabled (P0L[5..4] = `10'), the standard ST10 Bootstrap Loader is enabled and a variable is cleared to indicate that ABM is not enabled. If Alternate Boot mode is selected (P0L[5..4] = `01'), then, depending on signatures integrity checks, a predefined reset sequence is activated.
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Bootstrap loader
ST10F276Z5
5.7
Selective boot mode
The selective boot is a subcase of the Alternate Boot mode. When none of the signatures are correct, instead of executing the standard bootstrap loader (triggered by P0L.4 low at reset), an additional check is made. Address 00'1FFCh is read again with the following behavior:

If value is 0000h or FFFFh, a jump is performed to the standard bootstrap loader. Otherwise: - - High byte is disregarded. Low byte bits select which communication channel is enabled. Selective boot
Function UART selection `0': UART is not watched for a Start condition. `1': UART is watched for a Start condition. CAN1 selection `0': CAN1 is not watched for a Start condition. `1': CAN1 is watched for a Start condition. Reserved For upward compatibility, must be programmed to `0'
Table 38.
Bit
0
1
2..7
Therefore a value:

0xXX03 configures the Selective Bootstrap Loader to poll for RxD0 and CAN1_RxD. 0xXX01 configures the Selective Bootstrap Loader to poll only RxD0 (no boot via CAN). 0xXX02 configures the Selective Bootstrap Loader to poll only CAN1_RxD (no boot via UART). Other values allow the ST10F276Z5 to execute an endless loop into the Test-Flash.
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ST10F276Z5 Figure 13. Reset boot sequence
RSTIN 0 to 1
Bootstrap loader
Standard start
Yes (P0L[5..4] = `01') Boot mode? No (P0L[5..4] = `11')
Yes (P0L[5..4] = `10') No (P0L[5..4] = `other config.')
ST test modes
Software checks user reset vector (K1 is OK?) K1 is not OK
K1 is OK
Software Checks alternate reset vector (K2 is OK?)
K2 is not OK
K2 is OK Long jump to 09'0000h
Read 00'1FFCh SW RESET
Running from test Flash
ABM / User Flash
Start at 09'0000h
Std. Bootstrap Loader
Jump to Test-Flash
Selective Bootstrap Loader
Jump to Test-Flash
User Mode / User Flash
Start at 00'0000h
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Central processing unit (CPU)
ST10F276Z5
6
Central processing unit (CPU)
The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F276Z5 instructions can be executed in one instruction cycle which requires 31.25ns at 64 MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted. Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x 16-bit multiplication in 5 cycles and a 32/16-bit division in 10 cycles. The jump cache reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. The CPU uses a bank of 16 word registers to run the current context. This bank of General Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. The number of register banks is only restricted by the available Internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. Figure 14. CPU Block Diagram (MAC Unit not included)
16 CPU SP STKOV STKUN 512 Kbyte Flash memory 32 PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Pg. Ptrs Exec. Unit Instr. Ptr 4-Stage Pipeline MDH MDL Mul./Div.-HW Bit-Mask Gen. R15 2 Kbyte Internal RAM Bank n
ALU 16-Bit Barrel-Shift CP ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr.
General Purpose Registers
R0
Bank i
16
Bank 0
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ST10F276Z5
Central processing unit (CPU)
6.1
Multiplier-accumulator unit (MAC)
The MAC coprocessor is a specialized coprocessor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. The standard ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new coprocessor with up to 2 operands per instruction cycle. This new coprocessor (so-called MAC) contains a fast multiply-accumulate unit and a repeat unit. The coprocessor instructions extend the ST10 CPU instruction set with multiply, multiplyaccumulate, 32-bit signed arithmetic operations. Figure 15. MAC unit architecture
GPR Pointers * IDX0 Pointer IDX1 Pointer QR0 GPR Offset Register QR1 GPR Offset Register QX0 IDX Offset Register QX1 IDX Offset Register Concatenation 32 Mux Sign Extend MRW 0h 40 Repeat Unit Interrupt Controller ST10 CPU MSW Flags MAE Control Unit 40 8-bit Left/Right Shifter Mux 40 Scaler 08000h 40 40 0h 40 40 Mux 16 x 16 signed/unsigned Multiplier Operand 1 16 Operand 2 16
32
MCW
40 A B 40-bit Signed Arithmetic Unit 40 MAH MAL
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Central processing unit (CPU)
ST10F276Z5
6.2
Instruction set summary
The Table 39 lists the instructions of the ST10F276Z5. The detailed description of each instruction can be found in the "ST10 Family Programming Manual". Table 39. Standard instruction set summary
Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bit-wise AND, (word/byte operands) Bit-wise OR, (word/byte operands) Bit-wise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bit-wise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2 2/4 2/4 2/4 4 4
Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS
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ST10F276Z5 Table 39.
Central processing unit (CPU) Standard instruction set summary (continued)
Description Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle mode Enter Power-down mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 4 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2
Mnemonic J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP
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Central processing unit (CPU)
ST10F276Z5
6.3
MAC coprocessor specific instructions
The Table 40 lists the MAC instructions of the ST10F276Z5. The detailed description of each instruction can be found in the "ST10 Family Programming Manual". Note that all MAC instructions are encoded on 4 bytes. Table 40. MAC instruction set summary
Mnemonic CoABS CoADD(2) CoASHR(rnd) CoCMP CoLOAD(-,2) CoMAC(R,u,s,-,rnd) CoMACM(R)(u,s,-,rnd) CoMAX / CoMIN CoMOV CoMUL(u,s,-,rnd) CoNEG(rnd) CoNOP CoRND CoSHL / CoSHR CoSTORE CoSUB(2,R) Description Absolute Value of the Accumulator Addition Accumulator Arithmetic Shift Right & Optional Round Compare Accumulator with Operands Load Accumulator with Operands (Un)Signed/(Un)Signed Multiply-Accumulate & Optional Round (Un)Signed/(Un)Signed Multiply-Accumulate with Parallel Data Move & Optional Round Maximum / Minimum of Operands and Accumulator Memory to Memory Move (Un)Signed/(Un)Signed multiply & Optional Round Negate Accumulator & Optional Round No-Operation Round Accumulator Accumulator Logical Shift Left / Right Store a MAC Unit Register Substraction
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ST10F276Z5
External bus controller
7
External bus controller
All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes:

16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed 16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed 16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed 16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed
In demultiplexed bus modes addresses are output on PORT1 and data is input / output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input / output. Timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ALE and read / write delay) are programmable giving the choice of a wide range of memories and external peripherals. Up to four independent address windows may be defined (using register pairs ADDRSELx / BUSCONx) to access different resources and bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these four address windows are controlled by BUSCON0. Up to five external CS signals (four windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported by a `Ready' function. A HOLD / HLDA protocol is available for bus arbitration which shares external resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to'1' the slave mode is selected where pin HLDA is switched to input. This directly connects the slave controller to another master controller without glue logic. For applications which require less external memory space, the address space can be restricted to 1 Mbyte, 256 Kbytes or to 64 Kbytes. Port 4 outputs all eight address lines if an address space of 16M Bytes is used, otherwise four, two or no address lines. Chip select timing can be made programmable. By default (after reset), the CSx lines change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the SYSCON register the CSx lines change with the rising edge of ALE. The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register.
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Interrupt system
ST10F276Z5
8
Interrupt system
The interrupt response time for internal program execution is from 78 to 187.5 ns at 64 MHz CPU clock. The ST10F276Z5 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources (internal or external) to the microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single Byte or Word data transfer between any two memory locations with an additional increment of either the PEC source or destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F276Z5 has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. An interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit-field is dedicated to each existing interrupt source. Thanks to its related register, each source can be programmed to one of sixteen interrupt priority levels. Once starting to be processed by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Fast external interrupts may also have interrupt sources selected from other peripherals; for example the CANx controller receive signals (CANx_RxD) and I2C serial clock signal can be used to interrupt the system. Table 41 shows all the available ST10F276Z5 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Table 41. Interrupt sources
Request Flag CC0IR CC1IR CC2IR CC3IR CC4IR CC5IR Enable Flag CC0IE CC1IE CC2IE CC3IE CC4IE CC5IE Interrupt Vector CC0INT CC1INT CC2INT CC3INT CC4INT CC5INT Vector Location 00'0040h 00'0044h 00'0048h 00'004Ch 00'0050h 00'0054h Trap Number 10h 11h 12h 13h 14h 15h
Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5
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ST10F276Z5 Table 41. Interrupt sources (continued)
Request Flag CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR CC16IR CC17IR CC18IR CC19IR CC20IR CC21IR CC22IR CC23IR CC24IR CC25IR CC26IR CC27IR CC28IR CC29IR CC30IR CC31IR T0IR T1IR T7IR T8IR T2IR T3IR T4IR T5IR Enable Flag CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE CC16IE CC17IE CC18IE CC19IE CC20IE CC21IE CC22IE CC23IE CC24IE CC25IE CC26IE CC27IE CC28IE CC29IE CC30IE CC31IE T0IE T1IE T7IE T8IE T2IE T3IE T4IE T5IE Interrupt Vector CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT CC16INT CC17INT CC18INT CC19INT CC20INT CC21INT CC22INT CC23INT CC24INT CC25INT CC26INT CC27INT CC28INT CC29INT CC30INT CC31INT T0INT T1INT T7INT T8INT T2INT T3INT T4INT T5INT
Interrupt system
Source of Interrupt or PEC Service Request CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 CAPCOM Register 22 CAPCOM Register 23 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Register 28 CAPCOM Register 29 CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5
Vector Location 00'0058h 00'005Ch 00'0060h 00'0064h 00'0068h 00'006Ch 00'0070h 00'0074h 00'0078h 00'007Ch 00'00C0h 00'00C4h 00'00C8h 00'00CCh 00'00D0h 00'00D4h 00'00D8h 00'00DCh 00'00E0h 00'00E4h 00'00E8h 00'00ECh 00'00F0h 00'0110h 00'0114h 00'0118h 00'0080h 00'0084h 00'00F4h 00'00F8h 00'0088h 00'008Ch 00'0090h 00'0094h
Trap Number 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 44h 45h 46h 20h 21h 3Dh 3Eh 22h 23h 24h 25h
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Interrupt system Table 41. Interrupt sources (continued)
Request Flag T6IR CRIR ADCIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR PWMIR XP0IR XP1IR XP2IR XP3IR Enable Flag T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE PWMIE XP0IE XP1IE XP2IE XP3IE Interrupt Vector T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT PWMINT XP0INT XP1INT XP2INT XP3INT Vector Location 00'0098h 00'009Ch 00'00A0h 00'00A4h 00'00A8h 00'011Ch 00'00ACh 00'00B0h 00'00B4h 00'00B8h 00'00BCh 00'00FCh 00'0100h 00'0104h 00'0108h 00'010Ch
ST10F276Z5
Source of Interrupt or PEC Service Request GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error PWM Channel 0...3 See Paragraph 8.1 See Paragraph 8.1 See Paragraph 8.1 See Paragraph 8.1
Trap Number 26h 27h 28h 29h 2Ah 47h 2Bh 2Ch 2Dh 2Eh 2Fh 3Fh 40h 41h 42h 43h
Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any other program execution. Hardware trap services cannot not be interrupted by standard interrupt or by PEC interrupts.
8.1
X-Peripheral interrupt
The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some constraints on the implementation of the new functionality. In particular, the additional XPeripherals SSC1, ASC1, I2C, PWM1 and RTC need some resources to implement interrupt and PEC transfer capabilities. For this reason, a multiplexed structure for the interrupt management is proposed. In the next Figure 16, the principle is explained through a simple diagram, which shows the basic structure replicated for each of the four X-interrupt available vectors (XP0INT, XP1INT, XP2INT and XP3INT). It is based on a set of 16-bit registers XIRxSEL (x=0,1,2,3), divided in two portions each:

Byte High Byte Low
XIRxSEL[15:8] XIRxSEL[7:0]
Interrupt Enable bits Interrupt Flag bits
When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL register) define a mask which controls which sources will be associated with the unique
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ST10F276Z5
Interrupt system
available vector. If more than one source is enabled to issue the request, the service routine will have to take care to identify the real event to be serviced. This can easily be done by checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bits can also provide information about events which are not currently serviced by the interrupt controller (since masked through the enable bits), allowing an effective software management also in absence of the possibility to serve the related interrupt request: a periodic polling of the flag bits may be implemented inside the user application. Figure 16. X-Interrupt basic structure
7 0
Flag[7:0] IT Source 7 IT Source 6 IT Source 5 IT Source 4 IT Source 3 IT Source 2 IT Source 1 IT Source 0 Enable[7:0]
15 8
XIRxSEL[7:0] (x = 0, 1, 2, 3)
XPxIC.XPxIR (x = 0, 1, 2, 3)
XIRxSEL[15:8] (x = 0, 1, 2, 3)
The Table 42 summarizes the mapping of the different interrupt sources which shares the four X-interrupt vectors. Table 42. X-Interrupt detailed mapping
XP0INT CAN1 Interrupt CAN2 Interrupt I2C Receive I2C Transmit I2C Error SSC1 Receive SSC1 Transmit SSC1 Error ASC1 Receive ASC1 Transmit ASC1 Transmit Buffer x x x x x x x x x x x x x x x x x x x x x x x x x XP1INT XP2INT XP3INT x x
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Interrupt system Table 42. X-Interrupt detailed mapping (continued)
XP0INT ASC1 Error PLL Unlock / OWD PWM1 Channel 3...0
x
ST10F276Z5
XP1INT
XP2INT
XP3INT x
x x
8.2
Exception and error traps list
Table 43 shows all of the possible exceptions or error conditions that can arise during runtime. Table 43. Trap priorities
Trap Flag Trap Vector RESET RESET RESET NMI STKOF STKUF UNDOPC MACTRP PRTFLT ILLOPA ILLINA ILLBUS NMITRAP STOTRAP STUTRAP BTRAP BTRAP BTRAP BTRAP BTRAP BTRAP Vector Location 00'0000h 00'0000h 00'0000h 00'0008h 00'0010h 00'0018h 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h [002Ch - 003Ch] Any 0000h - 01FCh in steps of 4h Trap Number 00h 00h 00h 02h 04h 06h 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah [0Bh - 0Fh] Any [00h - 7Fh] Current CPU Priority Trap* Priority III III III II II II I I I I I I
Exception Condition Reset Functions(1): Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps(2): Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps(3): Undefined Opcode MAC Interruption Protected Instruction Fault Illegal word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction
1. The resets have the highest priority level and the same trap number. The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced. 2. Each class A traps has a dedicated trap number (and vector). They are prioritized in the second priority level. 3. All the class B traps have the same trap number (and vector) and the same lower priority compare to the class A traps and to the resets.
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ST10F276Z5
Capture / compare (CAPCOM) units
9
Capture / compare (CAPCOM) units
The ST10F276Z5 has two 16-channel CAPCOM units which support generation and control of timing sequences on up to 32 channels with a maximum resolution of 125 ns at 64 MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. Each of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare functions. Each of the 32 registers has one associated port pin which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture / compare register, specific actions will be taken based on the selected compare mode. The input frequencies fTx, for the timer input selector Tx, are determined as a function of the CPU clocks. The timer input frequencies, resolution and periods which result from the selected pre-scaler option in TxI when using a 40 MHz and 64 MHz CPU clock are listed in the Table 45 and Table 46 respectively. The numbers for the timer periods are based on a reload value of 0000h. Note that some numbers may be rounded to 3 significant figures.
Table 44.
Compare modes
Function Interrupt-only compare mode; several compare interrupts per timer period are possible Pin toggles on each compare match; several compare events per timer period are possible Interrupt-only compare mode; only one compare interrupt per timer period is generated
Compare modes Mode 0 Mode 1 Mode 2
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Capture / compare (CAPCOM) units Table 44. Compare modes (continued)
Function
ST10F276Z5
Compare modes Mode 3 Double Register mode
Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible.
Table 45.
CAPCOM timer input frequencies, resolutions and periods at 40 MHz
Timer Input Selection TxI
fCPU = 40 MHz 000b Pre-scaler for fCPU Input Frequency Resolution Period 8 5 MHz 200 ns 13.1 ms 001b 16 2.5 MHz 400 ns 26.2 ms 010b 32 1.25 MHz 0.8 s 52.4 ms 011b 64 625 kHz 1.6 s 104.8 ms 100b 128 312.5 kHz 3.2 s 209.7 ms 101b 256 156.25 kHz 6.4 s 419.4 ms 110b 512 78.125 kHz 12.8 s 838.9 ms 111b 1024 39.1 kHz 25.6 s 1.678 s
Table 46.
CAPCOM timer input frequencies, resolutions and periods at 64 MHz
Timer Input Selection TxI
fCPU = 64 MHz 000b Pre-scaler for fCPU Input Frequency Resolution Period 8 8 MHz 125 ns 8.2 ms 001b 16 4 MHz 250 ns 16.4 ms 010b 32 2 MHz 0.5 s 32.8 ms 011b 64 1 kHz 1.0 s 65.5 ms 100b 128 500 kHz 2.0 s 131.1 ms 101b 256 250 kHz 4.0 s 262.1 ms 110b 512 128 kHz 8.0 s 524.3 ms 111b 1024 64 kHz 16.0 s 1.049 s
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ST10F276Z5
General purpose timer unit
10
General purpose timer unit
The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2. Each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module.
10.1
GPT1
Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode. In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. In counter mode, the timer is clocked in reference to external events. Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. Table 47 and Table 48 list the timer input frequencies, resolution and periods for each prescaler option at 40 MHz and 64 MHz CPU clock respectively. In Incremental Interface mode, the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has output toggle latches (TxOTL) which changes state on each timer over flow / underflow. The state of this latch may be output on port pins (TxOUT) for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for high resolution of long duration measurements. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3.
Table 47.
GPT1 timer input frequencies, resolutions and periods at 40 MHz
Timer Input Selection T2I / T3I / T4I
fCPU = 40 MHz 000b Pre-scaler factor Input frequency Resolution Period maximum 8 5 MHz 200 ns 13.1 ms 001b 16 2.5 MHz 400 ns 26.2 ms 010b 32 1.25 MHz 0.8 s 52.4 ms 011b 64 625 kHz 1.6 s 104.8 ms 100b 128 101b 256 110b 512 111b 1024 39.1 kHz 25.6 s 1.678 s
312.5 kHz 156.25 kHz 78.125 kHz 3.2 s 209.7 ms 6.4 s 419.4 ms 12.8 s 838.9 ms
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General purpose timer unit Table 48. GPT1 timer input frequencies, resolutions and periods at 64 MHz
Timer Input Selection T2I / T3I / T4I fCPU = 64 MHz 000b Pre-scaler factor Input Freq Resolution Period maximum 8 8 MHz 125 ns 8.2 ms 001b 16 4 MHz 250 ns 16.4 ms 010b 32 2 MHz 0.5 s 32.8 ms 011b 64 1 kHz 1.0 s 65.5 ms 100b 128 500 kHz 2.0 s 131.1 ms 101b 256 250 kHz 4.0 s 262.1 ms 110b 512
ST10F276Z5
111b 1024 64 kHz 16.0 s 1.049 s
128 kHz 8.0 s 524.3 ms
Figure 17. Block diagram of GPT1
T2EUD CPU Clock T2IN
2n n=3...10 U/D
GPT1 Timer T2 T2 Mode Control
Reload Capture
Interrupt Request
CPU Clock T3IN T3EUD
2n n=3...10
T3 Mode Control
T3OUT GPT1 Timer T3
U/D Capture
T3OTL
T4IN CPU Clock T4EUD
2n n=3...10
T4 Mode Control
Reload
Interrupt Request GPT1 Timer T4 U/D Interrupt Request
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ST10F276Z5
General purpose timer unit
10.2
GPT2
The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental Interface mode. Table 49 and Table 50 list the timer input frequencies, resolution and periods for each prescaler option at 40 MHz and 64 MHz CPU clock respectively. Table 49. GPT2 timer input frequencies, resolutions and periods at 40 MHz
Timer Input Selection T5I / T6I fCPU = 40MHz 000b Pre-scaler factor Input Freq Resolution Period maximum 4 10 MHz 100 ns 001b 8 5 MHz 200 ns 010b 16 2.5 MHz 400 ns 011b 32 1.25 MHz 0.8 s 52.4 ms 100b 64 625 kHz 1.6 s 104.8 m s 101b 128 312.5 kHz 3.2 s 110b 256 156.25 kHz 6.4 s 111b 512 78.125 kHz 12.8 s
6.55 ms 13.1 ms 26.2 ms
209.7 m 419.4 ms 838.9 ms s
Table 50.
GPT2 timer input frequencies, resolutions and periods at 64 MHz
Timer Input Selection T5I / T6I
fCPU = 64MHz 000b Pre-scaler factor Input Freq Resolution Period maximum 4 16 MHz 62.5 ns 4.1 ms 001b 8 8 MHz 125 ns 8.2 ms 010b 16 4 MHz 250 ns 16.4 ms 011b 32 2 MHz 0.5 s 32.8 ms 100b 64 1 kHz 1.0 s 65.5 ms 101b 128 500 kHz 2.0 s 131.1 ms 110b 256 250 kHz 4.0 s 111b 512 128 kHz 8.0 s
262.1 ms 524.3 ms
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General purpose timer unit Figure 18. Block diagram of GPT2
T5EUD CPU Clock T5IN
U/D 2n n=2...9
ST10F276Z5
T5 Mode Control
GPT2 Timer T5
Clear Capture
Interrupt Request
CAPIN GPT2 CAPREL
Reload
Interrupt Request
Interrupt Request
Toggle FF
T6IN CPU Clock T6EUD
2n n=2...9
T6 Mode Control
GPT2 Timer T6
U/D
T60TL
T6OUT to CAPCOM Timers
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ST10F276Z5
PWM modules
11
PWM modules
Two pulse width modulation modules are available on ST10F276Z5: standard PWM0 and XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned or centre-aligned PWM. In addition, the PWM modules can generate PWM burst signals and single shot outputs. The Table 51 and Table 52 show the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM modules can generate interrupt requests. Figure 19. Block diagram of PWM module
PPx Period Register * Match
Comparator
Clock 1 Clock 2
Input Control
Run
* PTx 16-bit Up/Down Counter
Up/Down/ Clear Control Match
Comparator
Output Control Enable
POUTx
Shadow Register
Write Control
* User readable / writeable register
PWx Pulse Width Register *
Table 51.
Mode Mode 0 CPU Clock/1 CPU Clock/64 Mode 1 CPU Clock/1 CPU Clock/64
PWM unit frequencies and resolutions at 40 MHz CPU clock
Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
25 ns 1.6 s
156.25 kHz 2.44 kHz
39.1 kHz 610 Hz
9.77 kHz 152.6 Hz
2.44 Hz 38.15 Hz
610 Hz 9.54 Hz
25 ns 1.6 s
78.12 kHz 1.22 kHz
19.53 kHz 305.17 Hz
4.88 kHz 76.29 Hz
1.22 kHz 19.07 Hz
305.2Hz 4.77 Hz
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PWM modules Table 52.
Mode Mode 0 CPU Clock/1 CPU Clock/64 Mode 1 CPU Clock/1 CPU Clock/64 15.6 ns 1.0s 125 kHz 1.95 kHz 31.25 kHz 488.28 Hz 7.81 kHz 122.07 Hz 1.95 kHz 30.52 Hz 15.6 ns 1.0s 250 kHz 3.91 kHz 62.5 kHz 976.6 Hz 15.63 kHz 244.1 Hz 3.91Hz 61.01 Hz
ST10F276Z5 PWM unit frequencies and resolutions at 64 MHz CPU clock
Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
977 Hz 15.26 Hz
488.3 Hz 7.63 Hz
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ST10F276Z5
Parallel ports
12
12.1
Parallel ports
Introduction
The ST10F276Z5 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications. The ST10F276Z5 has nine groups of I/O lines gathered as follows:

Port 0 is a two time 8-bit port named P0L (Low as less significant byte) and P0H (high as most significant byte) Port 1 is a two time 8-bit port named P1L and P1H Port 2 is a 16-bit port Port 3 is a 15-bit port (P3.14 line is not implemented) Port 4 is a 8-bit port Port 5 is a 16-bit port input only Port 6, Port 7 and Port 8 are 8-bit ports
These ports may be used as general purpose bidirectional input or output, software controlled with dedicated registers. For example, the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured (bitwise) for push-pull or open drain operation using ODPx registers. The input threshold levels are programmable (TTL/CMOS) for all the ports. The logic level of a pin is clocked into the input latch once per state time, regardless whether the port is configured for input or output. The threshold is selected with PICON and XPICON registers control bits. A write operation to a port pin configured as an input causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. A readmodify-write operation reads the value of the pin, modifies it, and writes it back to the output latch. Writing to a pin configured as an output (DPx.y=`1') causes the output latch and the pin to have the written value, since the output buffer is enabled. Reading this pin returns the value of the output latch. A read-modify-write operation reads the value of the output latch, modifies it, and writes it back to the output latch, thus also modifying the level at the pin. I/O lines support an alternate function which is detailed in the following description of each port.
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Parallel ports
ST10F276Z5
12.2
12.2.1
I/Os special features
Open drain mode
Some of the I/O ports of ST10F276Z5 support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND wired logical function. This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections), and is controlled through the respective Open Drain Control Registers ODPx.
12.2.2
Input threshold control
The standard inputs of the ST10F276Z5 determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds. The Port Input Control registers PICON and XPICON are used to select these thresholds for each Byte of the indicated ports, this means the 8-bit ports P0L, P0H, P1L, P1H, P4, P7 and P8 are controlled by one bit each while ports P2, P3 and P5 are controlled by two bits each. All options for individual direction and output mode control are available for each pin, independent of the selected input threshold.
12.3
Alternate port functions
Each port line has one associated programmable alternate input or output function.
PORT0 and PORT1 may be used as address and data lines when accessing external memory. Besides, PORT1 provides also: - - Input capture lines 8 additional analog input channels to the A/D converter
Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM0 module, of the PWM1 module and of the ASC1. Port 2 is also used for fast external interrupt inputs and for timer 7 input. Port 3 includes the alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 4 outputs the additional segment address bit A23...A16 in systems where more than 64 Kbytes of memory are to be access directly. In addition, CAN1, CAN2 and I2C lines are provided. Port 5 is used as analog input channels of the A/D converter or as timer control signals. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals and the SSC1 lines.

If the alternate output function of a pin is to be used, the direction of this pin must be programmed for output (DPx.y=`1'), except for some signals that are used directly after reset and are configured automatically. Otherwise the pin remains in the high-impedance state and is not effected by the alternate output function. The respective port latch should hold a
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ST10F276Z5
Parallel ports
`1', because its output is ANDed with the alternate output data (except for PWM output signals). If the alternate input function of a pin is used, the direction of the pin must be programmed for input (DPx.y=`0') if an external device is driving the pin. The input direction is the default after reset. If no external device is connected to the pin, however, one can also set the direction for this pin to output. In this case, the pin reflects the state of the port output latch. Thus, the alternate input function reads the value stored in the port output latch. This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch. On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin. This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in the multiplexed external bus modes of PORT0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data. Obviously, this cannot be done through instructions. In these cases, the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled. To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output. There is one basic structure for all port lines with only an alternate input function. Port lines with only an alternate output function, however, have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode. All port lines that are not used for these alternate functions may be used as general purpose I/O lines.
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A/D converter
ST10F276Z5
13
A/D converter
A 10-bit A/D converter with 16+8 multiplexed input channels and a sample and hold circuit is integrated on-chip. An automatic self-calibration adjusts the A/D converter module to process parameter variations at each reset event. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. The ST10F276Z5 has 16+8 multiplexed input channels on Port 5 and Port 1. The selection between Port 5 and Port 1 is made via a bit in a XBus register. Refer to the User Manual for a detailed description. A different accuracy is guaranteed (Total Unadjusted Error) on Port 5 and Port 1 analog channels (with higher restrictions when overload conditions occur); in particular, Port 5 channels are more accurate than the Port 1 ones. Refer to Electrical Characteristic section for details. The A/D converter input bandwidth is limited by the achievable accuracy: supposing a maximum error of 0.5LSB (2mV) impacting the global TUE (TUE depends also on other causes), in worst case of temperature and process, the maximum frequency for a sine wave analog signal is around 7.5 kHz. Of course, to reduce the effect of the input signal variation on the accuracy down to 0.05LSB, the maximum input frequency of the sine wave shall be reduced to 800 Hz. If static signal is applied during sampling phase, series resistance shall not be greater than 20k (this taking into account eventual input leakage). It is suggested to not connect any capacitance on analog input pins, in order to reduce the effect of charge partitioning (and consequent voltage drop error) between the external and the internal capacitance: in case an RC filter is necessary the external capacitance must be greater than 10 nF to minimize the accuracy impact. Overrun error detection / protection is controlled by the ADDAT register. Either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. For applications which require less than 16+8 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the ST10F276Z5 supports different conversion modes:
Single channel single conversion: The analog level of the selected channel is sampled once and converted. The result of the conversion is stored in the ADDAT register. Single channel continuous conversion: The analog level of the selected channel is repeatedly sampled and converted. The result of the conversion is stored in the ADDAT register. Auto scan single conversion: The analog level of the selected channels are sampled once and converted. After each conversion the result is stored in the ADDAT register. The data can be transferred to the RAM by interrupt software management or using the powerful Peripheral Event Controller (PEC) data transfer. Auto scan continuous conversion: The analog level of the selected channels are repeatedly sampled and converted. The result of the conversion is stored in the ADDAT
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ST10F276Z5
A/D converter register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer.
Wait for ADDAT read mode: When using continuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the ADWR bit of ADCON control register must be activated. Then, until the ADDAT register is read, the new result is stored in a temporary buffer and the conversion is on hold. Channel injection mode: When using continuous modes, a selected channel can be converted in between without changing the current operating mode. The 10-bit data of the conversion are stored in ADRES field of ADDAT2. The current continuous mode remains active after the single conversion is completed.
A full calibration sequence is performed after a reset. This full calibration lasts up to 40.630 CPU clock cycles. During this time, the busy flag ADBSY is set to indicate the operation. It compensates the capacitance mismatch, so the calibration procedure does not need any update during normal operation. No conversion can be performed during this time: the bit ADBSY shall be polled to verify when the calibration is over, and the module is able to start a conversion.
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Serial channels
ST10F276Z5
14
Serial channels
Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided by up to four serial interfaces: two asynchronous / synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial channel (SSC0 and SSC1). Dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning. For transmission, reception and erroneous reception, separate interrupt vectors are provided for ASC0 and SSC0 serial channel. A more complex mechanism of interrupt sources multiplexing is implemented for ASC1 and SSC1 (XBUS mapped).
14.1
Asynchronous / synchronous serial interfaces
The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial communication between the ST10F276Z5 and other microcontrollers, microprocessors or external peripherals.
14.2
ASCx in asynchronous mode
In asynchronous mode, 8- or 9-bit data transfer, parity generation and the number of stop bits can be selected. Parity framing and overrun error detection is provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. Fullduplex communication up to 2M Bauds (at 64 MHz of fCPU) is supported in this mode.
Table 53.
ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz)
S0BRS = `0', fCPU = 40 MHz S0BRS = `1', fCPU = 40 MHz Baud rate (Baud) 833 333 112 000 56 000 38 400 19 200 9 600 4 800 2 400 1 200 600 300 102 Deviation Error 0.0% / 0.0% +6.3% / -7.0% +6.3% / -0.8% +3.3% / -1.4% +0.9% / -1.4% +0.9% / -0.2% +0.4% / -0.2% +0.1% / -0.2% +0.1% / -0.1% +0.1% / 0.0% 0.0% / 0.0% 0.0% / 0.0% Reload value (hex) 0000 / 0000 0006 / 0007 000D / 000E 0014 / 0015 002A / 002B 0055 / 0056 00AC / 00AD 015A / 015B 02B5 / 02B6 056B / 056C 0AD8 / 0AD9 1FE8 / 1FE9
Baud rate (Baud) 1 250 000 112 000 56 000 38 400 19 200 9 600 4 800 2 400 1 200 600 300 153
Deviation error 0.0% / 0.0% +1.5% / -7.0% +1.5% / -3.0% +1.7% / -1.4% +0.2% / -1.4% +0.2% / -0.6% +0.2% / -0.2% +0.2% / 0.0% 0.1% / 0.0% 0.0% / 0.0% 0.0% / 0.0% 0.0% / 0.0%
Reload value (hex) 0000 / 0000 000A / 000B 0015 / 0016 001F / 0020 0040 / 0041 0081 / 0082 0103 / 0104 0207 / 0208 0410 / 0411 0822 / 0823 1045 / 1046 1FE8 / 1FE9
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ST10F276Z5 Table 54.
Serial channels
ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz)
S0BRS = `0', fCPU = 64 MHz S0BRS = `1', fCPU = 64 MHz Baud rate (Baud) 1 333 333 112 000 56 000 38 400 19 200 9 600 4 800 2 400 1 200 600 300 163 Deviation error 0.0% / 0.0% +6.3% / -7.0% +6.3% / -0.8% +3.3% / -1.4% +0.9% / -1.4% +0.9% / -0.2% +0.4% / -0.2% +0.1% / -0.2% +0.1% / -0.1% +0.1% / 0.0% 0.0% / 0.0% 0.0% / 0.0% Reload value (hex) 0000 / 0000 000A / 000B 0016 / 0017 0021 / 0022 0044 / 0045 0089 / 008A 0114 / 0115 022A / 015B 0456 / 0457 08AD / 08AE 115B / 115C 1FF2 / 1FF3
Baud rate (Baud) 2 000 000 112 000 56 000 38 400 19 200 9 600 4 800 2 400 1 200 600 300 245
Deviation error 0.0% / 0.0% +1.5% / -7.0% +1.5% / -3.0% +1.7% / -1.4% +0.2% / -1.4% +0.2% / -0.6% +0.2% / -0.2% +0.2% / 0.0% 0.1% / 0.0% 0.0% / 0.0% 0.0% / 0.0% 0.0% / 0.0%
Reload value (hex) 0000 / 0000 0010 / 0011 0022 / 0023 0033 / 0034 0067 / 0068 00CF / 00D0 019F / 01A0 0340 / 0341 0681 / 0682 0D04 / 0D05 1A09 / 1A0A 1FE2 / 1FE3
Note:
The deviation errors given in the Table 53 and Table 54 are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency).
14.3
ASCx in synchronous mode
In synchronous mode, data is transmitted or received synchronously to a shift clock which is generated by the ST10F276Z5. Half-duplex communication up to 8M Baud (at 40 MHz of fCPU) is possible in this mode.
Table 55.
ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz)
S0BRS = `0', fCPU = 40 MHz S0BRS = `1', fCPU = 40 MHz Baud rate (Baud) 3 333 333 112 000 56 000 38 400 19 200 9 600 4 800 2 400 1 200 Deviation error 0.0% / 0.0% +2.6% / -0.8% +0.9% / -0.8% +0.9% / -0.2% +0.4% / -0.2% +0.1% / -0.2% +0.1% / -0.1% +0.1% / 0.0% 0.0% / 0.0% Reload value (hex) 0000 / 0000 001C / 001D 003A / 003B 0055 / 0056 00AC / 00AD 015A / 015B 02B5 / 02B6 056B / 056C 0AD8 / 0AD9
Baud rate (Baud) 5 000 000 112 000 56 000 38 400 19 200 9 600 4 800 2 400 1 200
Deviation error 0.0% / 0.0% +1.5% / -0.8% +0.3% / -0.8% +0.2% / -0.6% +0.2% / -0.2% +0.2% / 0.0% +0.1% / 0.0% 0.0% / 0.0% 0.0% / 0.0%
Reload value (hex) 0000 / 0000 002B / 002C 0058 / 0059 0081 / 0082 0103 / 0104 0207 / 0208 0410 / 0411 0822 / 0823 1045 / 1046
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Serial channels Table 55.
ST10F276Z5
ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz)
S0BRS = `0', fCPU = 40 MHz S0BRS = `1', fCPU = 40 MHz Baud rate (Baud) 600 407 Deviation error 0.0% / 0.0% 0.0% / 0.0% Reload value (hex) 15B2 / 15B3 1FFD / 1FFE
Baud rate (Baud) 900 612
Deviation error 0.0% / 0.0% 0.0% / 0.0%
Reload value (hex) 15B2 / 15B3 1FE8 / 1FE9
Table 56.
ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz)
S0BRS = `0', fCPU = 64 MHz S0BRS = `1', fCPU = 64 MHz Baud rate (Baud) 5 333 333 112 000 56 000 38 400 19 200 9 600 4 800 2 400 1 200 900 652 Deviation error 0.0% / 0.0% +1.3% / -0.8% +0.3% / -0.8% +0.6% / -0.1% +0.3% / -0.1% +0.1% / -0.1% 0.0% / -0.1% 0.0% / 0.0% 0.0% / 0.0% 0.0% / 0.0% 0.0% / 0.0% Reload value (hex) 0000 / 0000 002E / 002F 005E / 005F 0089 / 008A 0114 / 0115 022A / 022B 0456 / 0457 08AD / 08AE 115B / 115C 1724 / 1725 1FF2 / 1FF3
Baud rate (Baud) 8 000 000 112 000 56 000 38 400 19 200 9 600 4 800 2 400 1 200 977
Deviation error 0.0% / 0.0% +0.6% / -0.8% +0.6% / -0.1% +0.2% / -0.3% +0.2% / -0.1% +0.0% / -0.1% 0.0% / 0.0% 0.0% / 0.0% 0.0% / 0.0% 0.0% / 0.0%
Reload value (hex) 0000 / 0000 0046 / 0047 008D / 008E 00CF / 00D0 019F / 01A0 0340 / 0341 0681 / 0682 0D04 / 0D05 1A09 / 1A0A 1FFB / 1FFC
Note:
The deviation errors given in the Table 55 and Table 56 are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency)
14.4
High speed synchronous serial interfaces
The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible highspeed serial communication between the ST10F276Z5 and other microcontrollers, microprocessors or external peripherals. The SSCx supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSCx itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit Baud rate generator provides the SSCx with a separate serial clock signal. The serial channel SSCx has its own dedicated 16-bit Baud rate generator with 16-bit reload capability, allowing Baud rate generation independent from the timers. Table 57 and Table 58 list some possible Baud rates against the required reload values and the resulting bit times for 40 MHz and 64 MHz CPU clock respectively. The maximum is anyway limited to 8Mbaud.
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ST10F276Z5 Table 57. Synchronous baud rate and reload values (fCPU = 40 MHz)
Baud rate Reserved Can be used only with fCPU = 32 MHz (or lower) 6.6M Baud 5M Baud 2.5M Baud 1M Baud 100K Baud 10K Baud 1K Baud 306 Baud Bit Time ----150 ns 200 ns 400 ns 1 s 10 s 100 s 1 ms 3.26 ms
Serial channels
Reload value 0000h 0001h 0002h 0003h 0007h 0013h 00C7h 07CFh 4E1Fh FF4Eh
Table 58.
Synchronous baud rate and reload values (fCPU = 64 MHz)
Baud rate Bit Time ------125 ns 250 ns 1 s 10 s 100 s 1 ms 2.04 ms Reload value 0000h 0001h 0002h 0003h 0007h 001Fh 013Fh 0C7Fh 7CFFh FF9Eh
Reserved Can be used only with fCPU = 32 MHz (or lower) Can be used only with fCPU = 48 MHz (or lower) 8M Baud 4M Baud 1M Baud 100K Baud 10K Baud 1K Baud 489 Baud
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I2C interface
ST10F276Z5
15
I2C interface
The integrated I2C Bus Module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I2C Bus specification. The I2C Module can operate in slave mode, in master mode or in multi-master mode. It can receive and transmit data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s (both Standard and Fast I2C bus modes are supported). The module can generate three different types of interrupt:

Requests related to bus events, like start or stop events, arbitration lost, etc. Requests related to data transmission Requests related to data reception
These requests are issued to the interrupt controller by three different lines, and identified as Error, Transmit, and Receive interrupt lines. When the I2C module is enabled by setting bit XI2CEN in XPERCON register, pins P4.4 and P4.7 (where SCL and SDA are respectively mapped as alternate functions) are automatically configured as bidirectional open-drain: the value of the external pull-up resistor depends on the application. P4, DP4 and ODP4 cannot influence the pin configuration. When the I2C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O controlled by P4, DP4 and ODP4. The speed of the I2C interface may be selected between Standard mode (0 to 100 kHz) and Fast I2C mode (100 to 400 kHz).
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ST10F276Z5
CAN modules
16
CAN modules
The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active). It is based on the C-CAN specification. Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Because of duplication of the CAN controllers, the following adjustments are to be considered:
Same internal register addresses of both CAN controllers, but with base addresses differing in address bit A8; separate chip select for each CAN module. Refer to Chapter 4: Internal Flash memory. The CAN1 transmit line (CAN1_TxD) is the alternate function of the Port P4.6 pin and the receive line (CAN1_RxD) is the alternate function of the Port P4.5 pin. The CAN2 transmit line (CAN2_TxD) is the alternate function of the Port P4.7 pin and the receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin. Interrupt request lines of the CAN1 and CAN2 modules are connected to the XBUS interrupt lines together with other X-Peripherals sharing the four vectors. The CAN modules must be selected with corresponding CANxEN bit of XPERCON register before the bit XPEN of SYSCON register is set. The reset default configuration is: CAN1 enabled, CAN2 disabled.

Note:
If one or both CAN modules is used, Port 4 cannot be programmed to output all 8 segment address lines. Thus, only four segment address lines can be used, reducing the external memory space to 5 Mbytes (1 Mbyte per CS line).
16.1
Configuration support
It is possible that both CAN controllers are working on the same CAN bus, supporting together up to 64 message objects. In this configuration, both receive signals and both transmit signals are linked together when using the same CAN transceiver. This configuration is especially supported by providing open drain outputs for the CAN1_Txd and CAN2_TxD signals. The open drain function is controlled with the ODP4 register for port P4: in this way it is possible to connect together P4.4 with P4.5 (receive lines) and P4.6 with P4.7 (transmit lines configured to be configured as Open-Drain). The user is also allowed to map internally both CAN modules on the same pins P4.5 and P4.6. In this way, P4.4 and P4.7 may be used either as general purpose I/O lines, or used for I2C interface. This is possible by setting bit CANPAR of XMISC register. To access this register it is necessary to set bit XMISCEN of XPERCON register and bit XPEN of SYSCON register.
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CAN modules
ST10F276Z5
16.2
CAN bus configurations
Depending on application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F276Z5 is able to support these two cases.
Single CAN bus
The single CAN Bus multiple interfaces configuration may be implemented using two CAN transceivers as shown in Figure 20. Figure 20. Connection to single CAN bus via separate CAN transceivers
XMISC.CANPAR = 0 CAN1 RX TX CAN2 RX TX
P4.5
P4.6 P4.4
P4.7
CAN Transceiver CAN_H CAN_L
CAN Transceiver
CAN bus
The ST10F276Z5 also supports single CAN Bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in Figure 21. Thanks to the OR-Wired Connection, only one transceiver is required. In this case the design of the application must take in account the wire length and the noise environment. Figure 21. Connection to single CAN bus via common CAN transceivers
XMISC.CANPAR = 0 CAN1 RX TX +5 V P4.5 2.7kW P4.6 P4.4 OD P4.7 OD CAN2 RX TX
CAN Transceiver CAN_H CAN_L
CAN bus
OD = Open Drain Output
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ST10F276Z5
CAN modules
Multiple CAN bus
The ST10F276Z5 provides two CAN interfaces to support such kind of bus configuration as shown in Figure 22. Figure 22. Connection to two different CAN buses (e.g. for gateway application)
XMISC.CANPAR = 0 CAN1 RX TX CAN2 RX TX
P4.5
P4.6 P4.4
P4.7
CAN Transceiver CAN_H CAN_L CAN bus 1
CAN Transceiver CAN_H CAN_L CAN bus 2
Parallel mode
In addition to previous configurations, a parallel mode is supported. This is shown in Figure 23. Figure 23. Connection to one CAN bus with internal Parallel mode enabled
XMISC.CANPAR = 1 (Both CAN enabled)
CAN1 RX TX
CAN2 RX TX
P4.5
P4.6 P4.4
P4.7
CAN Transceiver CAN_H CAN_L
CAN bus
1. P4.4 and P4.7 when not used as CAN functions can be used as general purpose I/O while they cannot be used as external bus address lines.
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Real-time clock
ST10F276Z5
17
Real-time clock
The real-time clock is an independent timer, in which the clock is derived directly from the clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator) so that it can be kept on running even in Idle or Power-down mode (if enabled to). Registers access is implemented onto the XBUS. This module is designed with the following characteristics:

Generation of the current time and date for the system Cyclic time based interrupt, on Port2 external interrupts every 'RTC basic clock tick' and after n 'RTC basic clock ticks' (n is programmable) if enabled 58-bit timer for long term measurement Capability to exit the ST10 chip from Power-down mode (if PWDCFG of SYSCON set) after a programmed delay
The real-time clock is based on two main blocks of counters. The first block is a prescaler which generates a basic reference clock (for example a 1 second period). This basic reference clock is coming out of a 20-bit DIVIDER. This 20-bit counter is driven by an input clock derived from the on-chip CPU clock, pre-divided by a 1/64 fixed counter. This 20-bit counter is loaded at each basic reference clock period with the value of the 20-bit PRESCALER register. The value of the 20-bit RTCP register determines the period of the basic reference clock. A timed interrupt request (RTCSI) may be sent on each basic reference clock period. The second block of the RTC is a 32-bit counter that may be initialized with the current system time. This counter is driven with the basic reference clock signal. In order to provide an alarm function the contents of the counter is compared with a 32-bit alarm register. The alarm register may be loaded with a reference date. An alarm interrupt request (RTCAI), may be generated when the value of the counter matches the alarm register. The timed RTCSI and the alarm RTCAI interrupt requests can trigger a fast external interrupt via EXISEL register of port 2 and wake-up the ST10 chip when running Powerdown mode. Using the RTCOFF bit of RTCCON register, the user may switch off the clock oscillator when entering the Power-down mode. The last function implemented in the RTC is to switch off the main on-chip oscillator and the 32 kHz on chip oscillator if the ST10 enters the Power-down mode, so that the chip can be fully switched off (if RTC is disabled). At power on, and after Reset phase, if the presence of a 32 kHz oscillation on XTAL3 / XTAL4 pins is detected, then the RTC counter is driven by this low frequency reference clock: when Power-down mode is entered, the RTC can either be stopped or left running, and in both the cases the main oscillator is turned off, reducing the power consumption of the device to the minimum required to keep on running the RTC counter and relative reference oscillator. This is valid also if Standby mode is entered (switching off the main supply VDD), since both the RTC and the low power oscillator (32 kHz) are biased by the VSTBY. Vice versa, when at power on and after Reset, the 32 kHz is not present, the main oscillator drives the RTC counter, and since it is powered by the main power supply, it cannot be maintained running in Standby mode, while in Power-down mode the main oscillator is maintained running to provide the reference to the RTC module (if not disabled).
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ST10F276Z5
Watchdog timer
18
Watchdog timer
The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Therefore, the chip start-up procedure is always monitored. The software must be designed to service the watchdog timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components to be reset. Each of the different reset sources is indicated in the WDTCON register:

Watchdog Timer Reset in case of an overflow Software Reset in case of execution of the SRST instruction Short, Long and Power-On Reset in case of hardware reset (and depending of reset pulse duration and RPD pin configuration)
The indicated bits are cleared with the EINIT instruction. The source of the reset can be identified during the initialization phase. The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high Byte of the watchdog timer register can be set to a pre-specified reload value (stored in WDTREL). Each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced The Table 59 and Table 60 show the watchdog time range for 40 MHz and 64 MHz CPU clock respectively. Table 59. WDTREL reload value (fCPU = 40 MHz)
Prescaler for fCPU = 40 MHz Reload value in WDTREL 2 (WDTIN = `0') FFh 00h 12.8 s 3.277 ms 128 (WDTIN = `1') 819.2 s 209.7 ms
Table 60.
WDTREL reload value (fCPU = 64 MHz)
Prescaler for fCPU = 64 MHz
Reload value in WDTREL 2 (WDTIN = `0') FFh 00h 8 s 2.048 ms 128 (WDTIN = `1') 512 s 131.1 ms
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System reset
ST10F276Z5
19
System reset
System reset initializes the MCU in a predefined state. There are six ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 61. Table 61. Reset event definition(1)
Flag PONR RPD Status Low Low LHWR High Power-on
(2)
Reset Source Power-on reset Asynchronous Hardware reset Synchronous Long Hardware reset Synchronous Short Hardware reset Watchdog Timer reset Software reset
Conditions
tRSTIN > (1032 + 12) TCL + max(4 TCL, 500 ns) tRSTIN > max(4 TCL, 500 ns) tRSTIN (1032 + 12) TCL + max(4 TCL, 500 ns) WDT overflow SRST instruction execution
SHWR WDTR SWR
High
(3)
1. See next Section 19.1 for more details on minimum reset pulse duration. 2. RSTIN pulse should be longer than 500 ns (Filter) and than settling time for configuration of Port0. 3. The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to Section 19.4, Section 19.5 and Section 19.6).
19.1
Input filter
On RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all the spikes shorter than 50 ns. On the other side, a valid pulse shall be longer than 500 ns to grant that ST10 recognizes a reset command. In between 50 ns and 500 ns a pulse can either be filtered or recognized as valid, depending on the operating conditions and process variations. For this reason all minimum durations mentioned in this Chapter for the different kind of reset events shall be carefully evaluated taking into account of the above requirements. In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input reset pulse duration, the operating frequency is a key factor. Examples:

For a CPU clock of 64 MHz, 4 TCL is 31.25 ns, so it would be filtered. In this case the minimum becomes the one imposed by the filter (that is 500 ns). For a CPU clock of 4 MHz, 4 TCL is 500 ns. In this case the minimum from the formula is coherent with the limit imposed by the filter.
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ST10F276Z5
System reset
19.2
Asynchronous reset
An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the device is immediately (after the input filter delay) forced in reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it aborts all internal/external bus cycles, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high Port0 pins.
Note:
If an asynchronous reset occurs during a read or write phase in internal memories, the content of the memory itself could be corrupted: to avoid this, synchronous reset usage is strongly recommended.
Power-on reset
The asynchronous reset must be used during the power-on of the device. Depending on crystal or resonator frequency, the on-chip oscillator needs about 1 to 10 ms to stabilize (Refer to Electrical Characteristics Section), with an already stable VDD. The logic of the device does not need a stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the RPD pin must be held at low level until the device clock signal is stabilized and the system configuration value on Port0 is settled. At Power-on it is important to respect some additional constraints introduced by the start-up phase of the different embedded modules. In particular the on-chip voltage regulator needs at least 1 ms to stabilize the internal 1.8 V for the core logic: this time is computed from when the external reference (VDD) becomes stable (inside specification range, that is at least 4.5 V). This is a constraint for the application hardware (external voltage regulator): the RSTIN pin assertion shall be extended to guarantee the voltage regulator stabilization. A second constraint is imposed by the embedded FLASH. When booting from internal memory, starting from RSTIN releasing, it needs a maximum of 1 ms for its initialization: before that, the internal reset (RST signal) is not released, so the CPU does not start code execution in internal memory. Note: This is not true if external memory is used (pin EA held low during reset phase). In this case, once RSTIN pin is released, and after few CPU clock (Filter delay plus 3...8 TCL), the internal reset signal RST is released as well, so the code execution can start immediately after. Obviously, an eventual access to the data in internal Flash is forbidden before its initialization phase is completed: an eventual access during starting phase will return FFFFh (just at the beginning), while later 009Bh (an illegal opcode trap can be generated). At Power-on, the RSTIN pin shall be tied low for a minimum time that includes also the startup time of the main oscillator (tSTUP = 1 ms for resonator, 10 ms for crystal) and PLL synchronization time (tPSUP = 200s): this means that if the internal FLASH is used, the RSTIN pin could be released before the main oscillator and PLL are stable to recover some time in the start-up phase (FLASH initialization only needs stable V18, but does not need stable system clock since an internal dedicated oscillator is used).
Warning:
It is recommended to provide the external hardware with a current limitation circuitry. This is necessary to avoid permanent damages of the device during the power-on transient, when the capacitance on V18 pin is charged. For the on-chip voltage regulator functionality 10 nF are
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System reset
ST10F276Z5 sufficient: anyway, a maximum of 100 nF on V18 pin should not generate problems of over-current (higher value is allowed if current is limited by the external hardware). External current limitation is anyway recommended also to avoid risks of damage in case of temporary short between V18 and ground: the internal 1.8 V drivers are sized to drive currents of several tens of Ampere, so the current shall be limited by the external hardware. The limit of current is imposed by power dissipation considerations (Refer to Electrical Characteristics Section).
In next Figure 24 and Figure 25 Asynchronous Power-on timing diagrams are reported, respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded FLASH module when selected. Note: Never power the device without keeping RSTIN pin grounded: the device could enter in unpredictable states, risking also permanent damages.
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ST10F276Z5 Figure 24. Asynchronous power-on RESET (EA = 1)
System reset
1.2 ms (for resonator oscillation + PLL stabilization) 10.2 ms (for crystal oscillation + PLL stabilization) 1 ms (for on-chip VREG stabilization)
VDD
2 TCL
V18 XTAL1 RPD ...
RSTIN RSTF (After Filter) P0[15:13]
50 ns 500 ns 3..4 TCL transparent not t. not t.
P0[12:2]
transparent
not t.
P0[1:0]
not transparent
not t. 7 TCL
IBUS-CS (Internal) FLARST
1 ms
RST Latching point of Port0 for system start-up configuration
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System reset Figure 25. Asynchronous power-on RESET (EA = 0)
ST10F276Z5
1.2 ms (for resonator oscillation + PLL stabilization) 10.2 ms (for crystal oscillation + PLL stabilization) 1 ms (for on-chip VREG stabilization)
VDD
3..8 TCL1)
V18 XTAL1 RPD ...
RSTIN
50 ns 500 ns 3..4 TCL
RSTF (After Filter) P0[15:13] transparent
not t.
P0[12:2]
transparent
not t.
P0[1:0]
not transparent
not t. 8 TCL
ALE
RST Latching point of Port0 for system start-up configuration
1. 1. 3 to 8 TCL depending on clock source selection.
Hardware reset
The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggered by the hardware of the application. Internal hardware logic and application circuitry are described in Reset circuitry chapter and Figure 37, Figure 38 and Figure 39. It occurs when RSTIN is low and RPD is detected (or becomes) low as well.
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ST10F276Z5 Figure 26. Asynchronous hardware RESET (EA = 1)
(1)
System reset
2 TCL
RPD 50 ns 500 ns RSTIN 50 ns 500 ns 3..4 TCL not transparent transparent
RSTF (After Filter) P0[15:13]
not t.
not t.
P0[12:2]
not transparent
transparent
not t.
P0[1:0]
not transparent
not t. 7 TCL
IBUS-CS (internal) FLARST
1 ms
RST Latching point of Port0 for system start-up configuration
1. This timing can be longer than Port0 settling time + PLL synchronization (if needed, that is
P0(15:13) changed). It can be longer than 500 ns to take into account of Input Filter on RSTIN pin
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System reset Figure 27. Asynchronous hardware RESET (EA = 0)
1)
ST10F276Z5
3..8 TCL2)
RPD 50 ns 500 ns RSTIN 50 ns 500 ns 3..4 TCL not transparent transparent
RSTF (After Filter) P0[15:13]
not t.
P0[12:2]
not transparent
transparent
not t.
P0[1:0]
not transparent
not t. 8 TCL
ALE
RST Latching point of Port0 for system start-up configuration
1. This timing can be longer than Port0 settling time + PLL synchronization (if needed, that is
P0(15:13) changed). It can longer than 500ns to take into account of Input Filter on RSTIN pin.
2. 2. 3 to 8 TCL depending on clock source selection
Exit from asynchronous reset state
When the RSTIN pin is pulled high, the device restarts: as already mentioned, if internal FLASH is used, the restarting occurs after the embedded FLASH initialization routine is completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are driven to their inactive level. The device starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of asynchronous Hardware Reset sequence are summarized in Figure 26 and Figure 27.
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ST10F276Z5
System reset
19.3
Synchronous reset (warm reset)
A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high level. In order to properly activate the internal reset logic of the device, the RSTIN pin must be held low, at least, during 4 TCL (2 periods of CPU clock): refer also to Section 19.1 for details on minimum reset pulse duration. The I/O pins are set to high impedance and RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of 12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are cancelled and the current internal access cycle if any is completed. External bus cycle is aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON register was previously set by software. Note that this bit is always cleared on power-on or after a reset sequence.
Short and long synchronous reset
Once the first maximum 16 TCL are elapsed (4+12TCL), the internal reset sequence starts. It is 1024 TCL cycles long: at the end of it, and after other 8TCL the level of RSTIN is sampled (after the filter, see RSTF in the drawings): if it is already at high level, only Short Reset is flagged (Refer to Chapter 19: System reset for details on reset flags); if it is recognized still low, the Long reset is flagged as well. The major difference between Long and Short reset is that during the Long reset, also P0(15:13) become transparent, so it is possible to change the clock options.
Warning:
In case of a short pulse on RSTIN pin, and when Bidirectional reset is enabled, the RSTIN pin is held low by the internal circuitry. At the end of the 1024 TCL cycles, the RTSIN pin is released, but due to the presence of the input analog filter the internal input reset signal (RSTF in the drawings) is released later (from 50 to 500 ns). This delay is in parallel with the additional 8 TCL, at the end of which the internal input reset line (RSTF) is sampled, to decide if the reset event is Short or Long. In particular:

If 8 TCL > 500 ns (FCPU < 8 MHz), the reset event is always recognized as Short If 8 TCL < 500 ns (FCPU > 8 MHz), the reset event could be recognized either as Short or Long, depending on the real filter delay (between 50 and 500 ns) and the CPU frequency (RSTF sampled High means Short reset, RSTF sampled Low means Long reset). Note that in case a Long Reset is recognized, once the 8 TCL are elapsed, the P0(15:13) pins becomes transparent, so the system clock can be re-configured. The port returns not transparent 3-4TCL after the internal RSTF signal becomes high.
The same behavior just described, occurs also when unidirectional reset is selected and RSTIN pin is held low till the end of the internal sequence (exactly 1024TCL + max 16 TCL) and released exactly at that time. Note: When running with CPU frequency lower than 40 MHz, the minimum valid reset pulse to be recognized by the CPU (4 TCL) could be longer than the minimum analog filter delay (50ns); so it might happen that a short reset pulse is not filtered by the analog input filter, but on the other hand it is not long enough to trigger a CPU reset (shorter than 4 TCL): this would generate a FLASH reset but not a system reset. In this condition, the FLASH answers
113/239
System reset
ST10F276Z5
always with FFFFh, which leads to an illegal opcode and consequently a trap event is generated.
Exit from synchronous reset state
The reset sequence is extended until RSTIN level becomes high. Besides, it is internally prolonged by the FLASH initialization when EA=1 (internal memory selected). Then, the code execution restarts. The system configuration is latched from Port0, and ALE, RD and WR/WRL pins are driven to their inactive level. The device starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of synchronous reset sequence are summarized in Figures 28 and 29 where a Short Reset event is shown, with particular highlighting on the fact that it can degenerate into Long Reset: the two figures show the behavior when booting from internal or external memory respectively. Figure 30 and Figure 31 reports the timing of a typical synchronous Long Reset, again when booting from internal or external memory.
Synchronous reset and RPD pin
Whenever the RSTIN pin is pulled low (by external hardware or as a consequence of a Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance (if any) on RPD pin is slowly discharged through the internal weak pull-down. If the voltage level on RPD pin reaches the input low threshold (around 2.5 V), the reset event becomes immediately asynchronous. In case of hardware reset (short or long) the situation goes immediately to the one illustrated in Figure 26. There is no effect if RPD comes again above the input threshold: the asynchronous reset is completed coherently. To grant the normal completion of a synchronous reset, the value of the capacitance shall be big enough to maintain the voltage on RPD pin sufficient high along the duration of the internal reset sequence. For a Software or Watchdog reset events, an active synchronous reset is completed regardless of the RPD status. It is important to highlight that the signal that makes RPD status transparent under reset is the internal RSTF (after the noise filter).
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ST10F276Z5 Figure 28. Synchronous short / long hardware RESET (EA = 1)
4 TCL4) 12 TCL RSTIN 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent
1) 3)
System reset
< 1032 TCL
50 ns 500 ns
50 ns 500 ns
2 TCL
P0[12:2]
not t.
transparent
not t.
P0[1:0]
not transparent
not t. 7 TCL
IBUS-CS (Internal) 1 ms FLARST 1024 TCL RST At this time RSTF is sampled HIGH or LOW so it is SHORT or LONG reset RSTOUT 8 TCL
RPD
2)
200A Discharge
VRPD > 2.5 V Asynchronous Reset not entered
1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration. 2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5 V for 5 V operation),
the asynchronous reset is then immediately entered.
3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is
cleared after reset.
4. Minimum RSTIN low pulse duration shall also be longer than 500 ns to guarantee the pulse is not masked by the internal
filter (refer to Section 19.6).
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System reset Figure 29. Synchronous short / long hardware RESET (EA = 0)
4 TCL5) 12 TCL RSTIN 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent < 1032 TCL
ST10F276Z5
1) 50 ns 500 ns
4) 50 ns 500 ns
P0[12:2]
not t.
transparent
not t.
P0[1:0]
not transparent 3..8 TCL3)
not t. 8 TCL
ALE 1024 TCL RST At this time RSTF is sampled HIGH or LOW so it is SHORT or LONG reset RSTOUT 8 TCL
RPD 200 mA Discharge 2) VRPD > 2.5 V Asynchronous Reset not entered
1. 2. 3. 4.
RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5 V for 5 V operation), the asynchronous reset is then immediately entered. 3. 3 to 8 TCL depending on clock source selection. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. filter (refer to Section 19.6).
5. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal
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ST10F276Z5 Figure 30. Synchronous long hardware RESET (EA = 1)
4 TCL2) 12 TCL RSTIN 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent 50 ns 500 ns 50 ns 500 ns 1024+8 TCL
System reset
2 TCL
3..4 TCL transparent not t.
P0[12:2]
not t.
transparent
not t.
P0[1:0]
not transparent
not t. 7 TCL
IBUS-CS (Internal) 1 ms FLARST 1024+8 TCL RST At this time RSTF is sampled LOW so it is definitely LONG reset RSTOUT
RPD
1)
200A Discharge
VRPD > 2.5 V Asynchronous Reset not entered
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (around 2.5 V for 5 V operation), the asynchronous reset is then immediately entered. If RPD returns above the threshold, the reset is definitively taken as asynchronous. 2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 19.6).
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System reset Figure 31. Synchronous long hardware RESET (EA = 0)
4 TCL2) 12 TCL RSTIN 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent 50 ns 500 ns 50 ns 500 ns
ST10F276Z5
1024+8 TCL
3..4 TCL transparent not t.
P0[12:2]
transparent
not t.
P0[1:0]
not transparent 3..8 TCL
3)
not t. 8 TCL
ALE 1024+8 TCL RST At this time RSTF is sampled LOW so it is LONG reset RSTOUT
RPD
1)
200A Discharge
VRPD > 2.5 V Asynchronous Reset not entered
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5 V for 5 V operation), the asynchronous reset is then immediately entered. 2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 19.6). 3. 3. 3 to 8 TCL depending on clock source selection.
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ST10F276Z5
System reset
19.4
Software reset
A software reset sequence can be triggered at any time by the protected SRST (software reset) instruction. This instruction can be deliberately executed within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals system failure. On execution of the SRST instruction, the internal reset sequence is started. The microcontroller behavior is the same as for a synchronous short reset, except that only bits P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits P0.7...P0.2 are cleared (that is written at `1'). A Software reset is always taken as synchronous: there is no influence on Software Reset behavior with RPD status. In case Bidirectional Reset is selected, a Software Reset event pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled low even though Bidirectional Reset is selected. Refer to Figure 32 and Figure 33 for unidirectional SW reset timing, and to Figure 34, Figure 35 and Figure 36 for bidirectional.
19.5
Watchdog timer reset
When the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after the programmed wait states. When READY is sampled inactive (high) after the programmed wait states the running external bus cycle is aborted. Then the internal reset sequence is started. Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared (that is written at `1'). A Watchdog reset is always taken as synchronous: there is no influence on Watchdog Reset behavior with RPD status. In case Bidirectional Reset is selected, a Watchdog Reset event pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled low even though Bidirectional Reset is selected. Refer to Figure 32 and Figure 33 for unidirectional SW reset timing, and to Figure 34, Figure 35 and Figure 36 for bidirectional.
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System reset Figure 32. SW / WDT unidirectional RESET (EA = 1)
RSTIN 2 TCL not transparent
ST10F276Z5
P0[15:13]
P0[12:8]
transparent
not t.
P0[7:2]
not transparent
P0[1:0]
not transparent
not t. 7 TCL
IBUS-CS (Internal) 1 ms FLARST 1024 TCL RST
RSTOUT
Figure 33. SW / WDT unidirectional RESET (EA = 0)
RSTIN
P0[15:13]
not transparent
P0[12:8]
transparent
not t.
P0[7:2]
not transparent
P0[1:0]
not transparent
not t. 8 TCL
ALE 1024 TCL RST
RSTOUT
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ST10F276Z5
System reset
19.6
Bidirectional reset
As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization routine, until the protected EINIT instruction (End of Initialization) is completed. The Bidirectional Reset function is useful when external devices require a reset signal but cannot be connected to RSTOUT pin, because RSTOUT signal lasts during initialization. It is, for instance, the case of external memory running initialization routine before the execution of EINIT instruction. Bidirectional reset function is enabled by setting bit 3 (BDRSTEN) in SYSCON register. It only can be enabled during the initialization routine, before EINIT instruction is completed. When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal, for the duration of the internal reset sequence (synchronous/asynchronous hardware, synchronous software and synchronous watchdog timer resets). At the end of the internal reset sequence the pull down is released and:
After a Short Synchronous Bidirectional Hardware Reset, if RSTF is sampled low 8 TCL periods after the internal reset sequence completion (refer to Figure 28 and Figure 29), the Short Reset becomes a Long Reset. On the contrary, if RSTF is sampled high the device simply exits reset state. After a Software or Watchdog Bidirectional Reset, the device exits from reset. If RSTF remains still low for at least 4 TCL periods (minimum time to recognize a Short Hardware reset) after the reset exiting (refer to Figure 34 and Figure 35), the Software or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains low for less than 4 TCL, the device simply exits reset state.
The Bidirectional reset is not effective in case RPD is held low, when a Software or Watchdog reset event occurs. On the contrary, if a Software or Watchdog Bidirectional reset event is active and RPD becomes low, the RSTIN pin is immediately released, while the internal reset sequence is completed regardless of RPD status change (1024 TCL). Note: The bidirectional reset function is disabled by any reset sequence (bit BDRSTEN of SYSCON is cleared). To be activated again it must be enabled during the initialization routine.
WDTCON flags
Similarly to what already highlighted in the previous section when discussing about Short reset and the degeneration into Long reset, similar situations may occur when Bidirectional reset is enabled. The presence of the internal filter on RSTIN pin introduces a delay: when RSTIN is released, the internal signal after the filter (see RSTF in the drawings) is delayed, so it remains still active (low) for a while. It means that depending on the internal clock speed, a short reset may be recognized as a long reset: the WDTCON flags are set accordingly. Besides, when either Software or Watchdog bidirectional reset events occur, again when the RSTIN pin is released (at the end of the internal reset sequence), the RSTF internal signal (after the filter) remains low for a while, and depending on the clock frequency it is recognized high or low: 8TCL after the completion of the internal sequence, the level of RSTF signal is sampled, and if recognized still low a Hardware reset sequence starts, and WDTCON will flag this last event, masking the previous one (Software or Watchdog reset). Typically, a Short Hardware reset is recognized, unless the RSTIN pin (and consequently
121/239
System reset
ST10F276Z5
internal signal RSTF) is sufficiently held low by the external hardware to inject a Long Hardware reset. After this occurrence, the initialization routine is not able to recognize a Software or Watchdog bidirectional reset event, since a different source is flagged inside WDTCON register. This phenomenon does not occur when internal FLASH is selected during reset (EA = 1), since the initialization of the FLASH itself extend the internal reset duration well beyond the filter delay. Next Figure 34, Figure 35 and Figure 36 summarize the timing for Software and Watchdog Timer Bidirectional reset events: In particular Figure 36 shows the degeneration into Hardware reset. Figure 34. SW / WDT bidirectional RESET (EA=1)
RSTIN 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent 50 ns 500 ns
P0[12:8]
transparent
not t.
P0[7:2]
not transparent
P0[1:0]
not transparent 2 TCL
not t. 7 TCL
IBUS-CS (Internal) 1 ms FLARST 1024 TCL RST
RSTOUT
122/239
ST10F276Z5 Figure 35. SW / WDT bidirectional RESET (EA = 0)
System reset
RSTIN 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent 50 ns 500 ns
P0[12:8]
transparent
not t.
P0[7:2]
not transparent
P0[1:0]
not transparent
not t. 8 TCL
ALE 1024 TCL RST At this time RSTF is sampled HIGH so SW or WDT Reset is flagged in WDTCON
RSTOUT
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System reset
ST10F276Z5
Figure 36. SW / WDT bidirectional RESET (EA=0) followed by a HW RESET
RSTIN 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent 50 ns 500 ns
P0[12:8]
transparent
not t.
P0[7:2]
not transparent
P0[1:0]
not transparent
not t. 8 TCL
ALE 1024 TCL RST At this time RSTF is sampled LOW so HW Reset is entered
RSTOUT
19.7
Reset circuitry
Internal reset circuitry is described in Figure 39. The RSTIN pin provides an internal pull-up resistor of 50k to 250k (The minimum reset time must be calculated using the lowest value). It also provides a programmable (BDRSTEN bit of SYSCON register) pull-down to output internal reset state signal (synchronous reset, watchdog timer reset or software reset). This bidirectional reset function is useful in applications where external devices require a reset signal but cannot be connected to RSTOUT pin. This is the case of an external memory running codes before EINIT (end of initialization) instruction is executed. RSTOUT pin is pulled high only when EINIT is executed. The RPD pin provides an internal weak pull-down resistor which discharges external capacitor at a typical rate of 200A. If bit PWDCFG of SYSCON register is set, an internal pull-up resistor is activated at the end of the reset sequence. This pull-up will charge any capacitor connected on RPD pin. The simplest way to reset the device is to insert a capacitor C1 between RSTIN pin and VSS, and a capacitor between RPD pin and VSS (C0) with a pull-up resistor R0 between RPD pin and VDD. The input RSTIN provides an internal pull-up device equalling a resistor of 50k to 250k (the minimum reset time must be determined by the lowest value). Select C1 that produce a sufficient discharge time to permit the internal or external oscillator and / or internal PLL and the on-chip voltage regulator to stabilize.
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ST10F276Z5
System reset
To ensure correct power-up reset with controlled supply current consumption, specially if clock signal requires a long period of time to stabilize, an asynchronous hardware reset is required during power-up. For this reason, it is recommended to connect the external R0-C0 circuit shown in Figure 37 to the RPD pin. On power-up, the logical low level on RPD pin forces an asynchronous hardware reset when RSTIN is asserted low. The external pull-up R0 will then charge the capacitor C0. Note that an internal pull-down device on RPD pin is turned on when RSTIN pin is low, and causes the external capacitor (C0) to begin discharging at a typical rate of 100-200A. With this mechanism, after power-up reset, short low pulses applied on RSTIN produce synchronous hardware reset. If RSTIN is asserted longer than the time needed for C0 to be discharged by the internal pull-down device, then the device is forced in an asynchronous reset. This mechanism insures recovery from very catastrophic failure. Figure 37. Minimum external reset circuitry
RSTOUT RSTIN External Hardware + C1 a) Hardware Reset
VCC
R0 RPD +
b) For Power-up Reset (and Interruptible Power-down mode)
ST10F276Z5
C0
The minimum reset circuit of Figure 37 is not adequate when the RSTIN pin is driven from the device itself during software or watchdog triggered resets, because of the capacitor C1 that will keep the voltage on RSTIN pin above VIL after the end of the internal reset sequence, and thus will trigger an asynchronous reset sequence. Figure 38 shows an example of a reset circuit. In this example, R1-C1 external circuit is only used to generate power-up or manual reset, and R0-C0 circuit on RPD is used for power-up reset and to exit from Power-down mode. Diode D1 creates a wired-OR gate connection to the reset pin and may be replaced by open-collector Schmitt trigger buffer. Diode D2 provides a faster cycle time for repetitive power-on resets. R2 is an optional pull-up for faster recovery and correct biasing of TTL Open Collector drivers.
125/239
System reset Figure 38. System reset circuit
VDD VDD R2
ST10F276Z5
External Hardware D2 RSTIN VDD D1 o.d. R0 Open Drain Inverter RPD ST10F276Z5 + C0 External Reset Source + C1 R1
Figure 39. Internal (simplified) reset circuitry
EINIT Instruction Clr Q Set RSTOUT
Reset State Machine Clock VDD
Internal Reset Signal
Trigger Clr
SRST instruction watchdog overflow RSTIN BDRSTEN Reset Sequence (512 CPU Clock Cycles)
VDD Asynchronous Reset
RPD From/to Exit Powerdown Circuit
Weak Pulldown (~200A)
126/239
ST10F276Z5
System reset
19.8
Reset application examples
Next two timing diagrams (Figure 40 and Figure 41) provides additional examples of bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to Figure 38 for the external circuit scheme). Figure 40. Example of software or watchdog bidirectional reset (EA = 1)
EINIT
00h
not transparent
not transparent
not transparent
Latching point
Latching point
not transparent P0[1:0] not transparent Latching point
3..8 TCL
1Ch
Tfilter RST < 500 ns
< 4 TCL
Latching point
transparent
1 ms (C1 charge)
4 TCL
0Ch
transparent
1024 TCL (12.8 us)
not transparent
VIH
VIL
VIL
WDTCON [5:0]
RSTOUT
P0[15:13]
P0[12:8]
not transparent
RSTIN
RSTF ideal
RST
P0[7:2]
RPD
not transparent
Tfilter RST < 500 ns
04h
transparent
127/239
128/239
1024 TCL (12.8 us) 1 ms (C1 charge) 3..8 TCL EINIT
VIH VIL
System reset
RSTOUT
RSTIN Tfilter RST < 500 ns Tfilter RST < 500 ns
RSTF ideal
RPD
VIL
RST 4 TCL
WDTCON [5:0]
04h
0Ch
1Ch
< 4 TCL
00h
P0[15:13]
not transparent
transparent Latching point
not transparent
P0[12:8] not transparent
transparent Latching point
not transparent
P0[7:2] not transparent
transparent Latching point not transparent Latching point
not transparent
Figure 41. Example of software or watchdog bidirectional reset (EA = 0)
P0[1:0]
not transparent
ST10F276Z5
ST10F276Z5
System reset
19.9
Table 62.
Reset summary
A summary of the different reset events is reported in the table below. Reset event
Synch. Asynch. RSTIN min 1 ms (VREG) 1.2 ms (Reson. + PLL) 10.2 ms (Crystal + PLL) 1 ms (VREG) max WDTCON Flags SHWR LHWR WDTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PONR SWR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bidir RPD 0 EA 0
Event
N Asynch.
-
1
1
1
Power-on Reset 0 1 x 0 Hardware Reset (Asynchronous) 0 0 0 1 1 Short Hardware Reset (Synchronous) (1) 1 x x 0 1 0 1 0 1 N Asynch. x Y N Asynch. N Asynch. Y Y Asynch. Asynch.
FORBIDDEN NOT APPLICABLE
1
1
1
500 ns 500 ns 500 ns 500 ns max (4 TCL, 500 ns) max (4 TCL, 500 ns) max (4 TCL, 500 ns)
1032 + 12 TCL + max(4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns)
0 0 0 0 0 0
1 1 1 1 0 0
1 1 1 1 1 1
N Synch. N Synch.
1
0
Y
Synch.
0
0
1
Activated by internal logic for 1024 TCL max (4 TCL, 500 ns) 1 1 Y Synch. 1032 + 12 TCL + max(4 TCL, 500 ns)
0
0
1
Activated by internal logic for 1024 TCL 1 1 Long Hardware Reset (Synchronous) 0 1 N Synch. N Synch. 1032 + 12 TCL + max(4 TCL, 500 ns) 1032 + 12 TCL + max(4 TCL, 500 ns) 1032 + 12 TCL + max(4 TCL, 500 ns) 0 1 1 0 0 1 1 1 1
1
0
Y
Synch.
Activated by internal logic only for 1024 TCL 1032 + 12 TCL + max(4 TCL, 500 ns) 0 1 1
1
1
Y
Synch.
Activated by internal logic only for 1024 TCL
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System reset Table 62. Reset event (continued)
Synch. Asynch. RSTIN min Not activated Not activated Not activated Activated by internal logic for 1024 TCL Not activated Not activated Not activated Activated by internal logic for 1024 TCL max
ST10F276Z5
WDTCON Flags SHWR LHWR WDTR 0 0 0 0 1 1 1 1 X X X X P0L.0 Emu mode PONR SWR 1 1 1 1 1 1 1 1 X X X X P0L.1 Adapt mode
Event
x Software Reset (2) x 0 1 x Watchdog Reset (2) x 0 1
0 0 1 1 0 0 1 1
N Synch. N Synch. Y Y Synch. Synch.
Bidir
RPD
EA
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
N Synch. N Synch. Y Y Synch. Synch.
1. It can degenerate into a Long Hardware Reset and consequently differently flagged (see Section 19.3 for details). 2. When Bidirectional is active (and with RPD=0), it can be followed by a Short Hardware Reset and consequently differently flagged (see Section 19.6 for details).
The start-up configurations and some system features are selected on reset sequences as described in Table 63 and Figure 42. Table 63 describes what is the system configuration latched on PORT0 in the six different reset modes. Figure 42 summarizes the state of bits of PORT0 latched in RP0H, SYSCON, BUSCON0 registers. Table 63. PORT0 latched configuration for the different reset events
PORT0 Segm. Addr. Lines Clock Options Chip Selects
Reserved
Reserved P0L.3 X X X X
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0H.0
P0L.7
P0L.6
P0L.5
P0L.4
Sample event Software Reset Watchdog Reset Synchronous Short Hardware Reset Synchronous Long Hardware Reset Asynchronous Hardware Reset Asynchronous Power-On Reset
X X X
X X X
X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X
X X X X
X X X X
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P0L.2 -
Reserved
Bus Type
BSL
X: Pin is sampled -: Pin is not sampled
WR config.
ST10F276Z5 Figure 42. PORT0 bits latched into the different registers after reset
PORT0
H.7 H.6 CLKCFG H.5 H.4 H.3 H.2 H.1 H.0 WRC L.7 L.6 L.5 L.4 L.3 L.2 L.1 ADP L.0 EMU
System reset
SALSEL
CSSEL
BUSTYP
BSL
Res.
RP0H
CLKCFG SALSEL CSSEL WRC
Bootstrap Loader
Internal Control Logic
Clock Generator
Port 4 Logic
Port 6 Logic P0L.7
2
EA / VSTBY
P0L.7
SYSCON
ROMEN BYTDIS WRCFG
7 10
BUSCON0
BUS ALE ACT0 CTL0
9 7 6
BTYP
10
9
8
131/239
Power reduction modes
ST10F276Z5
20
Power reduction modes
Three different power reduction modes with different levels of power reduction have been implemented in the ST10F276Z5. In Idle mode only CPU is stopped, while peripheral still operate. In Power-down mode both CPU and peripherals are stopped. In Standby mode the main power supply (VDD) can be turned off while a portion of the internal RAM remains powered via VSTBY dedicated power pin. Idle and Power-down modes are software activated by a protected instruction and are terminated in different ways as described in the following sections. Standby mode is entered simply removing VDD, holding the MCU under reset state.
Note:
All external bus actions are completed before Idle or Power-down mode is entered. However, Idle or Power-down mode is not entered if READY is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access.
20.1
Idle mode
Idle mode is entered by running IDLE protected instruction. The CPU operation is stopped and the peripherals still run. Idle mode is terminate by any interrupt request. Whatever the interrupt is serviced or not, the instruction following the IDLE instruction will be executed after return from interrupt (RETI) instruction, then the CPU resumes the normal program.
20.2
Power-down mode
Power-down mode starts by running PWRDN protected instruction. Internal clock is stopped, all MCU parts are on hold including the watchdog timer. The only exception could be the real-time clock if opportunely programmed and one of the two oscillator circuits as a consequence (either the main or the 32 kHz on-chip oscillator). When real-time clock module is used, when the device is in Power-down mode a reference clock is needed. In this case, two possible configurations may be selected by the user application according to the desired level of power reduction:
A 32 kHz crystal is connected to the on-chip low-power oscillator (pins XTAL3 / XTAL4) and running. In this case the main oscillator is stopped when Power-down mode is entered, while the real-time clock continue counting using 32 kHz clock signal as reference. The presence of a running low-power oscillator is detected after the Poweron: this clock is immediately assumed (if present, or as soon as it is detected) as reference for the real-time clock counter and it will be maintained forever (unless specifically disabled via software). Only the main oscillator is running (XTAL1 / XTAL2 pins). In this case the main oscillator is not stopped when Power-down is entered, and the real-time clock continue counting using the main oscillator clock signal as reference.
There are two different operating Power-down modes: protected mode and interruptible mode.
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Power reduction modes
Before entering Power-down mode (by executing the instruction PWRDN), bit VREGOFF in XMISC register must be set. Note: Leaving the main voltage regulator active during Power-down may lead to unexpected behavior (ex: CPU wake-up) and power consumption higher than what specified.
20.2.1
Protected Power-down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is cleared. The Protected Power-down mode is only activated if the NMI pin is pulled low when executing PWRDN instruction (this means that the PWRD instruction belongs to the NMI software routine). This mode is only deactivated with an external hardware reset on RSTIN pin.
20.2.2
Interruptible Power-down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is set. The Interruptible Power-down mode is only activated if all the enabled Fast External Interrupt pins are in their inactive level. This mode is deactivated with an external reset applied to RSTIN pin or with an interrupt request applied to one of the Fast External Interrupt pins, or with an interrupt generated by the real-time clock, or with an interrupt generated by the activity on CAN's and I2C module interfaces. To allow the internal PLL and clock to stabilize, the RSTIN pin must be held low according the recommendations described in Chapter 19: System reset. An external RC circuit must be connected to RPD pin, as shown in the Figure 43. Figure 43. External RC circuitry on RPD pin
ST10F276Z5 VDD R0
220k minimum
RPD
+
C0
1F Typical
To exit Power-down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be asserted for at least 40 ns.
20.3
Standby mode
In Standby mode, it is possible to turn off the main VDD provided that VSTBY is available through the dedicated pin of the ST10F276Z5. To enter Standby mode it is mandatory to held the device under reset: once the device is under reset, the RAM is disabled (see XRAM2EN bit of XPERCON register), and its digital interface is frozen in order to avoid any kind of data corruption. A dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1.65 V in Standby mode) to bias all those circuits that shall remain active: the portion of XRAM (16Kbytes for the ST10F276Z5), the RTC counters and 32 kHz on-chip oscillator amplifier.
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In normal running mode (that is when main VDD is on) the VSTBY pin can be tied to VSS during reset to exercise the EA functionality associated with the same pin: the voltage supply for the circuitries which are usually biased with VSTBY (see in particular the 32 kHz oscillator used in conjunction with real-time clock module), is granted by the active main VDD. It must be noted that Standby mode can generate problems associated with the usage of different power supplies in CMOS systems; particular attention must be paid when the device I/O lines are interfaced with other external CMOS integrated circuits: if VDD of device becomes (for example in Standby mode) lower than the output level forced by the I/O lines of these external integrated circuits, the device could be directly powered through the inherent diode existing on device output driver circuitry. The same is valid for the device interfaced to active/inactive communication buses during Standby mode: current injection can be generated through the inherent diode. Furthermore, the sequence of turning on/off of the different voltage could be critical for the system (not only for the device). The device Standby mode current (ISTBY) may vary while VDD to VSTBY (and vice versa) transition occurs: some current flows between VDD and VSTBY pins. System noise on both VDD and VSTBY can contribute to increase this phenomenon.
20.3.1
Entering Standby mode
As already said, to enter Standby mode XRAM2EN bit in the XPERCON Register must be cleared: this allows to freeze immediately the RAM interface, avoiding any data corruption. As a consequence of a RESET event, the RAM Power Supply is switched to the internal low-voltage supply V18SB (derived from VSTBY through the low-power voltage regulator). The RAM interface will remain frozen until the bit XRAM2EN is set again by software initialization routine (at next exit from main VDD power-on reset sequence). Since V18 is falling down (as a consequence of VDD turning off), it can happen that the XRAM2EN bit is no longer able to guarantee its content (logic "0"), being the XPERCON Register powered by internal V18. This does not generate any problem, because the Standby mode switching dedicated circuit continues to confirm the RAM interface freezing, irrespective the XRAM2EN bit content; XRAM2EN bit status is considered again when internal V18 comes back over internal standby reference V18SB. If internal V18 becomes lower than internal standby reference (V18SB) of about 0.3 to 0.45 V with bit XRAM2EN set, the RAM Supply switching circuit is not active: in case of a temporary drop on internal V18 voltage versus internal V18SB during normal code execution, no spurious Standby mode switching can occur (the RAM is not frozen and can still be accessed). The ST10F276Z5 core module, generating the RAM control signals, is powered by internal V18 supply; during turning off transient these control signals follow the V18, while RAM is switched to V18SB internal reference. It could happen that a high level of RAM write strobe from device core (active low signal) is low enough to be recognized as a logic "0" by the RAM interface (due to V18 lower than V18SB): The bus status could contain a valid address for the RAM and an unwanted data corruption could occur. For this reason, an extra interface, powered by the switched supply, is used to prevent the RAM from this kind of potential corruption mechanism.
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Warning:
During power-off phase, it is important that the external hardware maintains a stable ground level on RSTIN pin, without any glitch, in order to avoid spurious exiting from reset status with unstable power supply.
20.3.2
Exiting Standby mode
After the system has entered the Standby mode, the procedure to exit this mode consists of a standard Power-on sequence, with the only difference that the RAM is already powered through V18SB internal reference (derived from VSTBY pin external voltage). It is recommended to held the device under RESET (RSTIN pin forced low) until external VDD voltage pin is stable. Even though, at the very beginning of the power-on phase, the device is maintained under reset by the internal low voltage detector circuit (implemented inside the main voltage regulator) till the internal V18 becomes higher than about 1.0 V, there is no warranty that the device stays under reset status if RSTIN is at high level during power ramp up. So, it is important the external hardware is able to guarantee a stable ground level on RSTIN along the power-on phase, without any temporary glitch. The external hardware shall be responsible to drive low the RSTIN pin until the VDD is stable, even though the internal LVD is active. Once the internal Reset signal goes low, the RAM (still frozen) power supply is switched to the main V18. At this time, everything becomes stable, and the execution of the initialization routines can start: XRAM2EN bit can be set, enabling the RAM.
20.3.3
Real-time clock and Standby mode
When Standby mode is entered (turning off the main supply VDD), the real-time clock counting can be maintained running in case the on-chip 32 kHz oscillator is used to provide the reference to the counter. This is not possible if the main oscillator is used as reference for the counter: Being the main oscillator powered by VDD, once this is switched off, the oscillator is stopped.
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20.3.4
Power reduction modes summary
In the following Table 64: Power reduction modes summary, a summary of the different Power reduction modes is reported. Table 64. Power reduction modes summary
STBY XRAM 32 kHz OSC Peripherals Main OSC XRAM biased biased biased biased biased off off VSTBY
CPU
Mode
on Idle on on Power-down on on off Standby off
on on on on on on on
off off off off off off off
on on off off off off off
off on off on on off on
RTC
VDD
run run off on off off off
off on off off on off on
biased biased biased biased biased biased biased
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Programmable output clock divider
21
Programmable output clock divider
A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of register SYSCON, it is possible to program the clock prescaling factor: in this way on P3.15 a prescaled value of the CPU clock can be output. When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15 does not output any clock signal, even though XCLKOUTDIV register is programmed.
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Register set
ST10F276Z5
22
Register set
This section summarizes all registers implemented in the ST10F276Z5, and explains the description format used in the chapters to describe the function and layout of the SFRs. For easy reference, the registers (except for GPRs) are sorted in two ways:

Sorted by address, to check which register is referenced by a given address. Sorted by register name, to find the location of a specific register.
22.1
Register description format
Throughout the document, the function and the layout of the different registers is described in a specific format. The example below explains this format. A word register is displayed as:
REG_NAME (A16h / A8h) 15 res. 14 res. 13 res. 12 res. 11 10 write res. only W SFR/ESFR/XBUS 9 hw bit RW 8 read only R 7 std bit RW 6 hw bit RW 5 4 bitfield RW 3 Reset value: ****h: 2 1 bitfield RW 0
Table 65.
Bit
Description
Function Explanation of bit(field) name Description of the functions controlled by this bit(field).
Bit(field) name
A byte register is displayed as:
REG_NAME (A16h / A8h) 15 14 13 12 11 10 SFR/ESFR/XBUS 9 8 7 RW 6 RW 5 4 RW 3 std bit hw bit bit field Reset value: - - **h: 2 1 RW 0 bit field
Elements: REG_NAME A16h / A8h SFR/ESFR/XBUS (* *) * * This register's name Long 16-bit address / Short 8-bit address Register space (SFR, ESFR or XBUS Register) Register contents after reset 0/1: defined X': undefined (undefined ('X') after power up) U': unchanged hwbit Bit that is set/cleared by hardware is written in bold
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22.2
General purpose registers (GPRs)
The GPRs form the register bank that the CPU works with. This register bank may be located anywhere within the internal RAM via the Context Pointer (CP). Due to the addressing mechanism, GPR banks reside only within the internal RAM. All GPRs are bitaddressable. Table 66.
Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
General purpose registers (GPRs)
Physical address (CP) + 0 (CP) + 2 (CP) + 4 (CP) + 6 (CP) + 8 (CP) + 10 (CP) + 12 (CP) + 14 (CP) + 16 (CP) + 18 (CP) + 20 (CP) + 22 (CP) + 24 (CP) + 26 (CP) + 28 (CP) + 30 8-bit addr ess F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh Description CPU general purpose (word) register R0 CPU general purpose (word) register R1 CPU general purpose (word) register R2 CPU general purpose (word) register R3 CPU general purpose (word) register R4 CPU general purpose (word) register R5 CPU general purpose (word) register R6 CPU general purpose (word) register R7 CPU general purpose (word) register R8 CPU general purpose (word) register R9 CPU general purpose (word) register R10 CPU general purpose (word) register R11 CPU general purpose (word) register R12 CPU general purpose (word) register R13 CPU general purpose (word) register R14 CPU general purpose (word) register R15 Reset value UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh
The first 8 GPRs (R7...R0) may also be accessed bytewise. Other than with SFRs, writing to a GPR byte does not affect the other byte of the respective GPR. The respective halves of the byte-accessible registers have special names: Table 67.
Name RL0 RH0 RL1 RH1 RL2 RH2
General purpose registers (GPRs) bytewise addressing
Physical address (CP) + 0 (CP) + 1 (CP) + 2 (CP) + 3 (CP) + 4 (CP) + 5 8-bit address F0h F1h F2h F3h F4h F5h Description CPU general purpose (byte) register RL0 CPU general purpose (byte) register RH0 CPU general purpose (byte) register RL1 CPU general purpose (byte) register RH1 CPU general purpose (byte) register RL2 CPU general purpose (byte) register RH2 Reset value UUh UUh UUh UUh UUh UUh
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Register set Table 67.
Name RL0 RL3 RH3 RL4 RH4 RL5 RH5 RL6 RH6 RL7 RH7
ST10F276Z5 General purpose registers (GPRs) bytewise addressing (continued)
Physical address (CP) + 0 (CP) + 6 (CP) + 7 (CP) + 8 (CP) + 9 (CP) + 10 (CP) + 11 (CP) + 12 (CP) + 13 (CP) + 14 (CP) + 15 8-bit address F0h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh Description CPU general purpose (byte) register RL0 CPU general purpose (byte) register RL3 CPU general purpose (byte) register RH3 CPU general purpose (byte) register RL4 CPU general purpose (byte) register RH4 CPU general purpose (byte) register RL5 CPU general purpose (byte) register RH5 CPU general purpose (byte) register RL6 CPU general purpose (byte) register RH6 CPU general purpose (byte) register RL7 CPU general purpose (byte) register RH7 Reset value UUh UUh UUh UUh UUh UUh UUh UUh UUh UUh UUh
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22.3
Special function registers ordered by name
The following table lists in alphabetical order all SFRs which are implemented in the ST10F276Z5. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". The system configuration is selected during reset. SYSCON reset value is 0000 0xx0 x000 0000b. Reset Value depends on different triggered reset event. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals. Some software controlled interrupt requests may be generated by setting the XPnIR bits (of XPnIC register) of the unused X-Peripheral nodes. Table 68.
Name ADCIC b ADCON b ADDAT ADDAT2 ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEIC b
Special function registers ordered by address
Physical address FF98h FFA0h FEA0h 8-bit address CCh D0h 50h Description A/D converter end of conversion interrupt control register A/D converter control register A/D converter result register A/D converter 2 result register Address select register 1 Address select register 2 Address select register 3 Address select register 4 Reset value - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
F0A0h E 50h FE18h FE1Ah FE1Ch FE1Eh FF9Ah 0Ch 0Dh 0Eh 0Fh CDh 86h 8Ah 8Bh 8Ch 8Dh 25h 40h BCh 41h 4Ah C6h 4Bh C7h
A/D converter overrun error interrupt control register - - 00h Bus configuration register 0 Bus configuration register 1 Bus configuration register 2 Bus configuration register 3 Bus configuration register 4 GPT2 capture/reload register CAPCOM register 0 CAPCOM register 0 interrupt control register CAPCOM register 1 CAPCOM register 10 CAPCOM register 10 interrupt control register CAPCOM register 11 CAPCOM register 11 interrupt control register 0xx0h 0000h 0000h 0000h 0000h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h - - 00h
BUSCON0 b FF0Ch BUSCON1 b FF14h BUSCON2 b FF16h BUSCON3 b FF18h BUSCON4 b FF1Ah CAPREL CC0 CC0IC b CC1 CC10 CC10IC b CC11 CC11IC b FE4Ah FE80h FF78h FE82h FE94h FF8Ch FE96h FF8Eh
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Register set Table 68.
Name CC12 CC12IC b CC13 CC13IC b CC14 CC14IC b CC15 CC15IC b CC16 CC16IC b CC17 CC17IC b CC18 CC18IC b CC19 CC19IC b CC1IC b CC2 CC20 CC20IC b CC21 CC21IC b CC22 CC22IC b CC23 CC23IC b CC24 CC24IC b CC25 CC25IC b CC26 CC26IC b CC27 CC27IC b
ST10F276Z5 Special function registers ordered by address (continued)
Physical address FE98h FF90h FE9Ah FF92h FE9Ch FF94h FE9Eh FF96h FE60h 8-bit address 4Ch C8h 4Dh C9h 4Eh CAh 4Fh CBh 30h Description CAPCOM register 12 CAPCOM register 12 interrupt control register CAPCOM register 13 CAPCOM register 13 interrupt control register CAPCOM register 14 CAPCOM register 14 interrupt control register CAPCOM register 15 CAPCOM register 15 interrupt control register CAPCOM register 16 CAPCOM register 16 interrupt control register CAPCOM register 17 CAPCOM register 17 interrupt control register CAPCOM register 18 CAPCOM register 18 interrupt control register CAPCOM register 19 CAPCOM register 19 interrupt control register CAPCOM register 1 interrupt control register CAPCOM register 2 CAPCOM register 20 CAPCOM register 20 interrupt control register CAPCOM register 21 CAPCOM register 21 interrupt control register CAPCOM register 22 CAPCOM register 22 interrupt control register CAPCOM register 23 CAPCOM register 23 interrupt control register CAPCOM register 24 CAPCOM register 24 interrupt control register CAPCOM register 25 CAPCOM register 25 interrupt control register CAPCOM register 26 CAPCOM register 26 interrupt control register CAPCOM register 27 CAPCOM register 27 interrupt control register Reset value 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h - - 00h 0000h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h
F160h E B0h FE62h 31h
F162h E B1h FE64h 32h
F164h E B2h FE66h 33h
F166h E B3h FF7Ah FE84h FE68h BDh 42h 34h
F168h E B4h FE6Ah 35h
F16Ah E B5h FE6Ch 36h
F16Ch E B6h FE6Eh 37h
F16Eh E B7h FE70h 38h
F170h E B8h FE72h 39h
F172h E B9h FE74h 3Ah
F174h E BAh FE76h 3Bh
F176h E BBh
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ST10F276Z5 Table 68.
Name CC28 CC28IC b CC29 CC29IC b CC2IC b CC3 CC30 CC30IC b CC31 CC31IC b CC3IC b CC4 CC4IC b CC5 CC5IC b CC6 CC6IC b CC7 CC7IC b CC8 CC8IC b CC9 CC9IC b CCM0 b CCM1 b CCM2 b CCM3 b CCM4 b CCM5 b CCM6 b CCM7 b CP CRIC b CSP
Register set Special function registers ordered by address (continued)
Physical address FE78h 8-bit address 3Ch Description CAPCOM register 28 CAPCOM register 28 interrupt control register CAPCOM register 29 CAPCOM register 29 interrupt control register CAPCOM register 2 interrupt control register CAPCOM register 3 CAPCOM register 30 CAPCOM register 30 interrupt control register CAPCOM register 31 CAPCOM register 31 interrupt control register CAPCOM register 3 interrupt control register CAPCOM register 4 CAPCOM register 4 interrupt control register CAPCOM register 5 CAPCOM register 5 interrupt control register CAPCOM register 6 CAPCOM register 6 interrupt control register CAPCOM register 7 CAPCOM register 7 interrupt control register CAPCOM register 8 CAPCOM register 8 interrupt control register CAPCOM register 9 CAPCOM register 9 interrupt control register CAPCOM mode control register 0 CAPCOM mode control register 1 CAPCOM mode control register 2 CAPCOM mode control register 3 CAPCOM mode control register 4 CAPCOM mode control register 5 CAPCOM mode control register 6 CAPCOM mode control register 7 CPU context pointer register GPT2 CAPREL interrupt control register CPU code segment pointer register (read-only) Reset value 0000h - - 00h 0000h - - 00h - - 00h 0000h 0000h - - 00h 0000h - - 00h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h FC00h - - 00h 0000h
F178h E BCh FE7Ah 3Dh
F184h E C2h FF7Ch FE86h FE7Ch BEh 43h 3Eh
F18Ch E C6h FE7Eh 3Fh
F194h E CAh FF7Eh FE88h FF80h FE8Ah FF82h FE8Ch FF84h FE8Eh FF86h FE90h FF88h FE92h FF8Ah FF52h FF54h FF56h FF58h FF22h FF24h FF26h FF28h FE10h FF6Ah FE08h BFh 44h C0h 45h C1h 46h C2h 47h C3h 48h C4h 49h C5h A9h AAh ABh ACh 91h 92h 93h 94h 08h B5h 04h
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Register set Table 68.
Name DP0H DP0L DP1H DP1L DP2 b DP3 b DP4 b DP6 b DP7 b DP8 b DPP0 DPP1 DPP2 DPP3 EMUCON EXICON b EXISEL b IDCHIP IDMANUF IDMEM IDPROG IDX0 b IDX1 b MAH MAL MCW b MDC b MDH MDL MRW b MSW b ODP2 b ODP3 b ODP4 b b b b b
ST10F276Z5 Special function registers ordered by address (continued)
Physical address 8-bit address Description P0H direction control register P0L direction control register P1H direction control register P1L direction control register Port 2 direction control register Port 3 direction control register Port 4 direction control register Port 6 direction control register Port 7 direction control register Port 8 direction control register CPU data page pointer 0 register (10-bit) CPU data page pointer 1 register (10-bit) CPU data page pointer 2 register (10-bit) CPU data page pointer 3 register (10-bit) Emulation control register External interrupt control register External interrupt source selection register Device identifier register (n is the device revision) Manufacturer identifier register On-chip memory identifier register Programming voltage identifier register MAC unit address pointer 0 MAC unit address pointer 1 MAC unit accumulator - High word MAC unit accumulator - Low word MAC unit control word CPU multiply divide control register CPU multiply divide register - High word CPU multiply divide register - Low word MAC unit repeat word MAC unit status word Port2 open drain control register Port3 open drain control register Port4 open drain control register Reset value - - 00h - - 00h - - 00h - - 00h 0000h 0000h - - 00h - - 00h - - 00h - - 00h 0000h 0001h 0002h 0003h - - XXh 0000h 0000h 114nh 0403h 30D0h 0040h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0200h 0000h 0000h - - 00h
F102h E 81h F100h E 80h F106h E 83h F104h E 82h FFC2h FFC6h FFCAh FFCEh FFD2h FFD6h FE00h FE02h FE04h FE06h FE0Ah E1h E3h E5h E7h E9h EBh 00h 01h 02h 03h 05h
F1C0h E E0h F1DAh E EDh F07Ch E 3Eh F07Eh E 3Fh F07Ah E 3Dh F078h E 3Ch FF08h FF0Ah FE5Eh FE5Ch FFDCh FF0Eh FE0Ch FE0Eh FFDAh FFDEh 84h 85h 2Fh 2Eh EEh 87h 06h 07h EDh EFh
F1C2h E E1h F1C6h E E3h F1CAh E E5h
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ST10F276Z5 Table 68.
Name ODP6 b ODP7 b ODP8 b ONES b P0H b P0L b P1H b P1L b P2 P3 P4 P5 b b b b
Register set Special function registers ordered by address (continued)
Physical address 8-bit address Description Port6 open drain control register Port7 open drain control register Port8 open drain control register Constant value 1's register (read-only) Port0 high register (upper half of PORT0) Port0 low register (lower half of PORT0) Port1 high register (upper half of PORT1) Port1 low register (lower half of PORT1) Port 2 register Port 3 register Port 4 register (8-bit) Port 5 register (read-only) Port 5 digital disable register Port 6 register (8-bit) Port 7 register (8-bit) Port 8 register (8-bit) PEC channel 0 control register PEC channel 1 control register PEC channel 2 control register PEC channel 3 control register PEC channel 4 control register PEC channel 5 control register PEC channel 6 control register PEC channel 7 control register Port input threshold control register PWM module period register 0 PWM module period register 1 PWM module period register 2 PWM module period register 3 CPU program status word PWM module up/down counter 0 PWM module up/down counter 1 PWM module up/down counter 2 PWM module up/down counter 3 Reset value - - 00h - - 00h - - 00h FFFFh - - 00h - - 00h - - 00h - - 00h 0000h 0000h - - 00h XXXXh 0000h - - 00h - - 00h - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
F1CEh E E7h F1D2h E E9h F1D6h E EBh FF1Eh FF02h FF00h FF06h FF04h FFC0h FFC4h FFC8h FFA2h FFA4h FFCCh FFD0h FFD4h FEC0h FEC2h FEC4h FEC6h FEC8h FECAh FECCh FECEh 8Fh 81h 80h 83h 82h E0h E2h E4h D1h D2h E6h E8h EAh 60h 61h 62h 63h 64h 65h 66h 67h
P5DIDIS b P6 P7 P8 b b b
PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PICON b PP0 PP1 PP2 PP3 PSW b PT0 PT1 PT2 PT3
F1C4h E E2h F038h E 1Ch F03Ah E 1Dh F03Ch E 1Eh F03Eh E 1Fh FF10h 88h
F030h E 18h F032h E 19h F034h E 1Ah F036h E 1Bh
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Register set Table 68.
Name PW0 PW1 PW2 PW3
ST10F276Z5 Special function registers ordered by address (continued)
Physical address FE30h FE32h FE34h FE36h 8-bit address 18h 19h 1Ah 1Bh 98h 99h Description PWM module pulse width register 0 PWM module pulse width register 1 PWM module pulse width register 2 PWM module pulse width register 3 PWM module control register 0 PWM module control register 1 PWM Module interrupt control register MAC unit offset register R0 MAC unit offset register R1 MAC unit Offset Register X0 MAC unit offset register X1 System start-up configuration register (read-only) Reset value 0000h 0000h 0000h 0000h 0000h 0000h - - 00h 0000h 0000h 0000h 0000h - - XXh
PWMCON0 b FF30h PWMCON1 b FF32h PWMIC b QR0 QR1 QX0 QX1 RP0H S0BG S0CON b S0EIC b S0RBUF S0RIC b S0TBIC b S0TBUF S0TIC b SP SSCBR SSCCON b SSCEIC b SSCRB SSCRIC b SSCTB SSCTIC b STKOV STKUN SYSCON b T0 T01CON b b
F17Eh E BFh F004h E 02h F006h E 03h F000h E 00h F002h E 01h F108h E 84h FEB4h FFB0h FF70h FEB2h FF6Eh 5Ah D8h B8h 59h B7h
Serial channel 0 baud rate generator reload register 0000h Serial channel 0 control register Serial channel 0 error interrupt control register Serial channel 0 receive buffer register (read-only) Serial channel 0 receive interrupt control register Serial channel 0 transmit buffer interrupt control register Serial channel 0 transmit buffer register (write-only) Serial channel 0 transmit interrupt control register CPU system stack pointer register SSC baud rate register SSC control register SSC error interrupt control register SSC receive buffer (read-only) SSC receive interrupt control register SSC transmit buffer (write-only) SSC transmit interrupt control register CPU stack overflow pointer register CPU stack underflow pointer register CPU system configuration register CAPCOM timer 0 register CAPCOM timer 0 and timer 1 control register 0000h - - 00h - - XXh - - 00h - - 00h 0000h - - 00h FC00h 0000h 0000h - - 00h XXXXh - - 00h 0000h - - 00h FA00h FC00h 0xx0h 0000h 0000h
F19Ch E CEh FEB0h FF6Ch FE12h 58h B6h 09h
F0B4h E 5Ah FFB2h FF76h D9h BBh
F0B2h E 59h FF74h BAh
F0B0h E 58h FF72h FE14h FE16h FF12h FE50h FF50h B9h 0Ah 0Bh 89h 28h A8h
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ST10F276Z5 Table 68.
Name T0IC b T0REL T1 T1IC b T1REL T2 T2CON b T2IC b T3 T3CON b T3IC b T4 T4CON b T4IC b T5 T5CON b T5IC b T6 T6CON b T6IC b T7 T78CON b T7IC b T7REL T8 T8IC b T8REL TFR b WDT WDTCON b XADRS3 XP0IC b XP1IC b XP2IC b
Register set Special function registers ordered by address (continued)
Physical address FF9Ch FE54h FE52h FF9Eh FE56h FE40h FF40h FF60h FE42h FF42h FF62h FE44h FF44h FF64h FE46h FF46h FF66h FE48h FF48h FF68h 8-bit address CEh 2Ah 29h CFh 2Bh 20h A0h B0h 21h A1h B1h 22h A2h B2h 23h A3h B3h 24h A4h B4h Description CAPCOM timer 0 interrupt control register CAPCOM timer 0 reload register CAPCOM timer 1 register CAPCOM timer 1 interrupt control register CAPCOM timer 1 reload register GPT1 timer 2 register GPT1 timer 2 control register GPT1 timer 2 interrupt control register GPT1 timer 3 register GPT1 timer 3 control register GPT1 timer 3 interrupt control register GPT1 timer 4 register GPT1 timer 4 control register GPT1 timer 4 interrupt control register GPT2 timer 5 register GPT2 timer 5 control register GPT2 timer 5 interrupt control register GPT2 timer 6 register GPT2 timer 6 control register GPT2 timer 6 interrupt control register CAPCOM timer 7 register CAPCOM timer 7 and 8 control register CAPCOM timer 7 interrupt control register CAPCOM timer 7 reload register CAPCOM timer 8 register CAPCOM timer 8 interrupt control register CAPCOM timer 8 reload register Trap flag register Watchdog timer register (read-only) Watchdog timer control register XPER address select register 3 See Section 8.1 See Section 8.1 See Section 8.1 Reset value - - 00h 0000h 0000h - - 00h 0000h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h 0000h 00xxh 800Bh - - 00h - - 00h - - 00h
F050h E 28h FF20h 90h
F17Ah E BDh F054h E 2Ah F052h E 29h F17Ch E BEh F056h E 2Bh FFACh FEAEh FFAEh D6h 57h D7h
F01Ch E 0Eh F186h E C3h F18Eh E C7h F196h E CBh
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Register set Table 68.
Name XP3IC b XPERCON ZEROS b
ST10F276Z5 Special function registers ordered by address (continued)
Physical address 8-bit address See Section 8.1 XPER configuration register Constant value 0's register (read-only) Description Reset value - - 00h - - 05h 0000h
F19Eh E CFh F024h E 12h FF1Ch 8Eh
22.4
Special function registers ordered by address
The following table lists by order of their physical addresses all SFRs which are implemented in the ST10F276Z5. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Table 69.
Name QX0 QX1 QR0 QR1 XADRS3 XPERCON PT0 PT1 PT2 PT3 PP0 PP1 PP2 PP3 T7 T8 T7REL T8REL IDPROG IDMEM IDCHIP
Special function registers ordered by address
Physical address F000h E F002h E F004h E F006h E F01Ch E F024h E F030h E F032h E F034h E F036h E F038h E F03Ah E F03Ch E F03Eh E F050h E F052h E F054h E F056h E F078h E F07Ah E F07Ch E 8-bit address 00h 01h 02h 03h 0Eh 12h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 28h 29h 2Ah 2Bh 3Ch 3Dh 3Eh Description MAC unit offset register X0 MAC unit offset register X1 MAC unit offset register R0 MAC unit offset register R1 XPER address select register 3 XPER configuration register PWM module up/down counter 0 PWM module up/down counter 1 PWM module up/down counter 2 PWM module up/down counter 3 PWM module period register 0 PWM module period register 1 PWM module period register 2 PWM module period register 3 CAPCOM timer 7 register CAPCOM timer 8 register CAPCOM timer 7 reload register CAPCOM timer 8 reload register Programming voltage identifier register On-chip memory identifier register Device identifier register (n is the device revision) Reset value 0000h 0000h 0000h 0000h 800Bh - - 05h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0040h 30D0h 114nh
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ST10F276Z5 Table 69.
Name IDMANUF ADDAT2 SSCTB SSCRB SSCBR DP0L DP0H DP1L DP1H RP0H b b b b b
Register set Special function registers ordered by address (continued)
Physical address F07Eh E F0A0h E F0B0h E F0B2h E F0B4h E F100h E F102h E F104h E F106h E F108h E F160h E F162h E F164h E F166h E F168h E F16Ah E F16Ch E F16Eh E F170h E F172h E F174h E F176h E F178h E F17Ah E F17Ch E F17Eh E F184h E F186h E F18Ch E F18Eh E F194h E F196h E F19Ch E 8-bit address 3Fh 50h 58h 59h 5Ah 80h 81h 82h 83h 84h B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C2h C3h C6h C7h CAh CBh CEh Description Manufacturer identifier register A/D converter 2 result register SSC transmit buffer (write-only) SSC receive buffer (read-only) SSC baud rate register P0L direction control register P0H direction control register P1L direction control register P1H direction control register System start-up configuration register (read-only) CAPCOM register 16 interrupt control register CAPCOM register 17 interrupt control register CAPCOM register 18 interrupt control register CAPCOM register 19 interrupt control register CAPCOM register 20 interrupt control register CAPCOM register 21 interrupt control register CAPCOM register 22 interrupt control register CAPCOM register 23 interrupt control register CAPCOM register 24 interrupt control register CAPCOM register 25 interrupt control register CAPCOM register 26 interrupt control register CAPCOM register 27 interrupt control register CAPCOM register 28 interrupt control register CAPCOM timer 7 interrupt control register CAPCOM timer 8 interrupt control register PWM module interrupt control register CAPCOM register 29 interrupt control register See Section 8.1 CAPCOM register 30 interrupt control register See Section 8.1 CAPCOM register 31 interrupt control register See Section 8.1 Serial channel 0 transmit buffer interrupt control register. Reset value 0403h 0000h 0000h XXXXh 0000h - - 00h - - 00h - - 00h - - 00h - - XXh - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h
CC16IC b CC17IC b CC18IC b CC19IC b CC20IC b CC21IC b CC22IC b CC23IC b CC24IC b CC25IC b CC26IC b CC27IC b CC28IC b T7IC b T8IC b PWMIC b CC29IC b XP0IC b CC30IC b XP1IC b CC31IC b XP2IC b S0TBIC b
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Register set Table 69.
Name XP3IC b EXICON b ODP2 b PICON b ODP3 b ODP4 b ODP6 b ODP7 b ODP8 b EXISEL b DPP0 DPP1 DPP2 DPP3 CSP EMUCON MDH MDL CP SP STKOV STKUN ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 PW0 PW1 PW2 PW3 T2 T3 T4 T5
ST10F276Z5 Special function registers ordered by address (continued)
Physical address F19Eh E F1C0h E F1C2h E F1C4h E F1C6h E F1CAh E F1CEh E F1D2h E F1D6h E F1DAh E FE00h FE02h FE04h FE06h FE08h FE0Ah FE0Ch FE0Eh FE10h FE12h FE14h FE16h FE18h FE1Ah FE1Ch FE1Eh FE30h FE32h FE34h FE36h FE40h FE42h FE44h FE46h 8-bit address CFh E0h E1h E2h E3h E5h E7h E9h EBh EDh 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 18h 19h 1Ah 1Bh 20h 21h 22h 23h See Section 8.1 External interrupt control register Port2 open drain control register Port input threshold control register Port3 open drain control register Port4 open drain control register Port6 open drain control register Port7 open drain control register Port8 open drain control register External interrupt source selection register CPU data page pointer 0 register (10-bit) CPU data page pointer 1 register (10-bit) CPU data page pointer 2 register (10-bit) CPU data page pointer 3 register (10-bit) CPU code segment pointer register (read-only) Emulation control register CPU multiply divide register - High word CPU multiply divide register - Low word CPU context pointer register CPU system stack pointer register CPU stack overflow pointer register CPU stack underflow pointer register Address select register 1 Address select register 2 Address select register 3 Address select register 4 PWM module pulse width register 0 PWM module pulse width register 1 PWM module pulse width register 2 PWM module pulse width register 3 GPT1 timer 2 register GPT1 timer 3 register GPT1 timer 4 register GPT2 timer 5 register Description Reset value - - 00h 0000h 0000h - - 00h 0000h - - 00h - - 00h - - 00h - - 00h 0000h 0000h 0001h 0002h 0003h 0000h - - XXh 0000h 0000h FC00h FC00h FA00h FC00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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ST10F276Z5 Table 69.
Name T6 CAPREL T0 T1 T0REL T1REL MAL MAH CC16 CC17 CC18 CC19 CC20 CC21 CC22 CC23 CC24 CC25 CC26 CC27 CC28 CC29 CC30 CC31 CC0 CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9
Register set Special function registers ordered by address (continued)
Physical address FE48h FE4Ah FE50h FE52h FE54h FE56h FE5Ch FE5Eh FE60h FE62h FE64h FE66h FE68h FE6Ah FE6Ch FE6Eh FE70h FE72h FE74h FE76h FE78h FE7Ah FE7Ch FE7Eh FE80h FE82h FE84h FE86h FE88h FE8Ah FE8Ch FE8Eh FE90h FE92h 8-bit address 24h 25h 28h 29h 2Ah 2Bh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h Description GPT2 timer 6 register GPT2 capture/reload register CAPCOM timer 0 register CAPCOM timer 1 register CAPCOM timer 0 reload register CAPCOM timer 1 reload register MAC unit accumulator - Low word MAC unit accumulator - High word CAPCOM register 16 CAPCOM register 17 CAPCOM register 18 CAPCOM register 19 CAPCOM register 20 CAPCOM register 21 CAPCOM register 22 CAPCOM register 23 CAPCOM register 24 CAPCOM register 25 CAPCOM register 26 CAPCOM register 27 CAPCOM register 28 CAPCOM register 29 CAPCOM register 30 CAPCOM register 31 CAPCOM register 0 CAPCOM register 1 CAPCOM register 2 CAPCOM register 3 CAPCOM register 4 CAPCOM register 5 CAPCOM register 6 CAPCOM register 7 CAPCOM register 8 CAPCOM register 9 Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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Register set Table 69.
Name CC10 CC11 CC12 CC13 CC14 CC15 ADDAT WDT S0TBUF S0RBUF S0BG PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 P0L b P0H b P1L b P1H b IDX0 b IDX1 b BUSCON0 b MDC b PSW b SYSCON b BUSCON1 b BUSCON2 b BUSCON3 b BUSCON4 b
ST10F276Z5 Special function registers ordered by address (continued)
Physical address FE94h FE96h FE98h FE9Ah FE9Ch FE9Eh FEA0h FEAEh FEB0h FEB2h FEB4h FEC0h FEC2h FEC4h FEC6h FEC8h FECAh FECCh FECEh FF00h FF02h FF04h FF06h FF08h FF0Ah FF0Ch FF0Eh FF10h FF12h FF14h FF16h FF18h FF1Ah 8-bit address 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 57h 58h 59h 5Ah 60h 61h 62h 63h 64h 65h 66h 67h 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh Description CAPCOM register 10 CAPCOM register 11 CAPCOM register 12 CAPCOM register 13 CAPCOM register 14 CAPCOM register 15 A/D converter result register Watchdog timer register (read-only) Serial channel 0 transmit buffer register (write-only) Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Serial channel 0 receive buffer register (read-only) - - XXh Serial channel 0 baud rate generator reload register PEC channel 0 control register PEC channel 1 control register PEC channel 2 control register PEC channel 3 control register PEC channel 4 control register PEC channel 5 control register PEC channel 6 control register PEC channel 7 control register Port0 low register (lower half of PORT0) Port0 high register (upper half of PORT0) Port1 low register (lower half of PORT1) Port1 high register (upper half of PORT1) MAC unit address pointer 0 MAC unit address pointer 1 Bus configuration register 0 CPU multiply divide control register CPU program status word CPU system configuration register Bus configuration register 1 Bus configuration register 2 Bus configuration register 3 Bus configuration register 4 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h - - 00h - - 00h - - 00h - - 00h 0000h 0000h 0xx0h 0000h 0000h 0xx0h 0000h 0000h 0000h 0000h
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ST10F276Z5 Table 69.
Name ZEROS b ONES b T78CON b CCM4 b CCM5 b CCM6 b CCM7 b
Register set Special function registers ordered by address (continued)
Physical address FF1Ch FF1Eh FF20h FF22h FF24h FF26h FF28h 8-bit address 8Eh 8Fh 90h 91h 92h 93h 94h 98h 99h A0h A1h A2h A3h A4h A8h A9h AAh ABh ACh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh Description Constant value 0's register (read-only) Constant value 1's register (read-only) CAPCOM timer 7 and 8 control register CAPCOM mode control register 4 CAPCOM mode control register 5 CAPCOM mode control register 6 CAPCOM mode control register 7 PWM module control register 0 PWM module control register 1 GPT1 timer 2 control register GPT1 timer 3 control register GPT1 timer 4 control register GPT2 timer 5 control register GPT2 timer 6 control register CAPCOM timer 0 and timer 1 control register CAPCOM mode control register 0 CAPCOM mode control register 1 CAPCOM mode control register 2 CAPCOM mode control register 3 GPT1 timer 2 interrupt control register GPT1 timer 3 interrupt control register GPT1 timer 4 interrupt control register GPT2 timer 5 interrupt control register GPT2 timer 6 interrupt control register GPT2 CAPREL interrupt control register Reset value 0000h FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h
PWMCON0 b FF30h PWMCON1 b FF32h T2CON b T3CON b T4CON b T5CON b T6CON b T01CON b CCM0 b CCM1 b CCM2 b CCM3 b T2IC b T3IC b T4IC b T5IC b T6IC b CRIC b S0TIC b S0RIC b S0EIC b SSCTIC b SSCRIC b SSCEIC b CC0IC b CC1IC b CC2IC b FF40h FF42h FF44h FF46h FF48h FF50h FF52h FF54h FF56h FF58h FF60h FF62h FF64h FF66h FF68h FF6Ah FF6Ch FF6Eh FF70h FF72h FF74h FF76h FF78h FF7Ah FF7Ch
Serial channel 0 transmit interrupt control register - - 00h Serial channel 0 receive interrupt control register Serial channel 0 error interrupt control register SSC transmit interrupt control register SSC receive interrupt control register SSC error interrupt control register CAPCOM register 0 interrupt control register CAPCOM register 1 interrupt control register CAPCOM register 2 interrupt control register - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h
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Register set Table 69.
Name CC3IC b CC4IC b CC5IC b CC6IC b CC7IC b CC8IC b CC9IC b CC10IC b CC11IC b CC12IC b CC13IC b CC14IC b CC15IC b ADCIC b ADEIC b T0IC b T1IC b ADCON b P5 b
ST10F276Z5 Special function registers ordered by address (continued)
Physical address FF7Eh FF80h FF82h FF84h FF86h FF88h FF8Ah FF8Ch FF8Eh FF90h FF92h FF94h FF96h FF98h FF9Ah FF9Ch FF9Eh FFA0h FFA2h FFA4h FFACh FFAEh FFB0h FFB2h FFC0h FFC2h FFC4h FFC6h FFC8h FFCAh FFCCh FFCEh FFD0h 8-bit address BFh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D6h D7h D8h D9h E0h E1h E2h E3h E4h E5h E6h E7h E8h Description CAPCOM register 3 interrupt control register CAPCOM register 4 interrupt control register CAPCOM register 5 interrupt control register CAPCOM register 6 interrupt control register CAPCOM register 7 interrupt control register CAPCOM register 8 interrupt control register CAPCOM register 9 interrupt control register CAPCOM register 10 interrupt control register CAPCOM register 11 interrupt control register CAPCOM register 12 interrupt control register CAPCOM register 13 interrupt control register CAPCOM register 14 interrupt control register CAPCOM register 15 interrupt control register A/D converter end of conversion interrupt control register A/D converter overrun error interrupt control register CAPCOM timer 0 interrupt control register CAPCOM timer 1 interrupt control register A/D converter control register Port 5 register (read-only) Port 5 digital disable register Trap flag register Watchdog timer control register Serial channel 0 control register SSC control register Port 2 register Port 2 direction control register Port 3 register Port 3 direction control register Port 4 register (8-bit) Port 4 direction control register Port 6 register (8-bit) Port 6 direction control register Port 7 register (8-bit) Reset value - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h 0000h XXXXh 0000h 0000h 00xxh 0000h 0000h 0000h 0000h 0000h 0000h - - 00h - - 00h - - 00h - - 00h - - 00h
P5DIDIS b TFR b WDTCON b S0CON b SSCCON b P2 b
DP2 b P3 b
DP3 b P4 b
DP4 b P6 b
DP6 b P7 b
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ST10F276Z5 Table 69.
Name DP7 b P8 b
Register set Special function registers ordered by address (continued)
Physical address FFD2h FFD4h FFD6h FFDAh FFDCh FFDEh 8-bit address E9h EAh EBh EDh EEh EFh Description Port 7 direction control register Port 8 register (8-bit) Port 8 direction control register MAC unit repeat word MAC unit control word MAC unit status word Reset value - - 00h - - 00h - - 00h 0000h 0000h 0200h
DP8 b MRW b MCW b MSW b
22.5
X-registers sorted by name
The following table lists by order of their names all X-Bus registers which are implemented in the ST10F276Z5. Although also physically mapped on X-Bus memory space, the Flash control registers are listed in a separate section,.
Note:
The X-registers are not bit-addressable. Table 70.
Name CAN1BRPER CAN1BTR CAN1CR CAN1EC CAN1IF1A1 CAN1IF1A2 CAN1IF1CM CAN1IF1CR CAN1IF1DA1 CAN1IF1DA2 CAN1IF1DB1 CAN1IF1DB2 CAN1IF1M1 CAN1IF1M2 CAN1IF1MC CAN1IF2A1 CAN1IF2A2 CAN1IF2CM CAN1IF2CR
X-Registers ordered by name
Physical address EF0Ch EF06h EF00h EF04h EF18h EF1Ah EF12h EF10h EF1Eh EF20h EF22h EF24h EF14h EF16h EF1Ch EF48h EF4Ah EF42h EF40h Description CAN1: BRP extension register CAN1: Bit timing register CAN1: CAN control register CAN1: Error counter CAN1: IF1 arbitration 1 CAN1: IF1 arbitration 2 CAN1: IF1 command mask CAN1: IF1 command request CAN1: IF1 data A 1 CAN1: IF1 data A 2 CAN1: IF1 data B 1 CAN1: IF1 data B 2 CAN1: IF1 mask 1 CAN1: IF1 mask 2 CAN1: IF1 message control CAN1: IF2 arbitration 1 CAN1: IF2 arbitration 2 CAN1: IF2 command mask CAN1: IF2 command request Reset value 0000h 2301h 0001h 0000h 0000h 0000h 0000h 0001h 0000h 0000h 0000h 0000h FFFFh FFFFh 0000h 0000h 0000h 0000h 0001h
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Register set Table 70.
Name CAN1IF2DA1 CAN1IF2DA2 CAN1IF2DB1 CAN1IF2DB2 CAN1IF2M1 CAN1IF2M2 CAN1IF2MC CAN1IP1 CAN1IP2 CAN1IR CAN1MV1 CAN1MV2 CAN1ND1 CAN1ND2 CAN1SR CAN1TR CAN1TR1 CAN1TR2 CAN2BRPER CAN2BTR CAN2CR CAN2EC CAN2IF1A1 CAN2IF1A2 CAN2IF1CM CAN2IF1CR CAN2IF1DA1 CAN2IF1DA2 CAN2IF1DB1 CAN2IF1DB2 CAN2IF1M1 CAN2IF1M2 CAN2IF1MC CAN2IF2A1
ST10F276Z5 X-Registers ordered by name (continued)
Physical address EF4Eh EF50h EF52h EF54h EF44h EF46h EF4Ch EFA0h EFA2h EF08h EFB0h EFB2h EF90h EF92h EF02h EF0Ah EF80h EF82h EE0Ch EE06h EE00h EE04h EE18h EE1Ah EE12h EE10h EE1Eh EE20h EE22h EE24h EE14h EE16h EE1Ch EE48h Description CAN1: IF2 data A 1 CAN1: IF2 data A 2 CAN1: IF2 data B 1 CAN1: IF2 data B 2 CAN1: IF2 mask 1 CAN1: IF2 mask 2 CAN1: IF2 message control CAN1: interrupt pending 1 CAN1: interrupt pending 2 CAN1: interrupt register CAN1: Message valid 1 CAN1: Message valid 2 CAN1: New data 1 CAN1: New data 2 CAN1: Status register CAN1: Test register CAN1: Transmission request 1 CAN1: Transmission request 2 CAN2: BRP extension register CAN2: Bit timing register CAN2: CAN control register CAN2: Error counter CAN2: IF1 arbitration 1 CAN2: IF1 arbitration 2 CAN2: IF1 command mask CAN2: IF1 command request CAN2: IF1 data A 1 CAN2: IF1 data A 2 CAN2: IF1 data B 1 CAN2: IF1 data B 2 CAN2: IF1 mask 1 CAN2: IF1 mask 2 CAN2: IF1 message control CAN2: IF2 arbitration 1 Reset value 0000h 0000h 0000h 0000h FFFFh FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 00x0h 0000h 0000h 0000h 2301h 0001h 0000h 0000h 0000h 0000h 0001h 0000h 0000h 0000h 0000h FFFFh FFFFh 0000h 0000h
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ST10F276Z5 Table 70.
Name CAN2IF2A2 CAN2IF2CM CAN2IF2CR CAN2IF2DA1 CAN2IF2DA2 CAN2IF2DB1 CAN2IF2DB2 CAN2IF2M1 CAN2IF2M2 CAN2IF2MC CAN2IP1 CAN2IP2 CAN2IR CAN2MV1 CAN2MV2 CAN2ND1 CAN2ND2 CAN2SR CAN2TR CAN2TR1 CAN2TR2 I2CCCR1 I2CCCR2 I2CCR I2CDR I2COAR1 I2COAR2 I2CSR1 I2CSR2 RTCAH RTCAL RTCCON RTCDH RTCDL
Register set X-Registers ordered by name (continued)
Physical address EE4Ah EE42h EE40h EE4Eh EE50h EE52h EE54h EE44h EE46h EE4Ch EEA0h EEA2h EE08h EEB0h EEB2h EE90h EE92h EE02h EE0Ah EE80h EE82h EA06h EA0Eh EA00h EA0Ch EA08h EA0Ah EA02h EA04h ED14h ED12h ED00H ED0Ch ED0Ah Description CAN2: IF2 arbitration 2 CAN2: IF2 command mask CAN2: IF2 command request CAN2: IF2 data A 1 CAN2: IF2 data A 2 CAN2: IF2 data B 1 CAN2: IF2 data B 2 CAN2: IF2 mask 1 CAN2: IF2 mask 2 CAN2: IF2 message control CAN2: Interrupt pending 1 CAN2: Interrupt pending 2 CAN2: Interrupt register CAN2: Message valid 1 CAN2: Message valid 2 CAN2: New data 1 CAN2: New data 2 CAN2: Status register CAN2: Test register CAN2: Transmission request 1 CAN2: Transmission request 2 I2C Clock control register 1 I2C Clock control register 2 I2C Control register I2C Data register I2C Own address register 1 I2C Own address register 2 I2C Status register 1 I2C Status register 2 RTC Alarm register high byte RTC Alarm register low byte RTC Control register RTC Divider counter high byte RTC Divider counter low byte Reset value 0000h 0000h 0001h 0000h 0000h 0000h 0000h FFFFh FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 00x0h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXXXh XXXXh 000Xh XXXXh XXXXh
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Register set Table 70.
Name RTCH RTCL RTCPH RTCPL XCLKOUTDIV XEMU0 XEMU1 XEMU2 XEMU3 XIR0CLR XIR0SEL XIR0SET XIR1CLR XIR1SEL XIR1SET XIR2CLR XIR2SEL XIR2SET XIR3CLR XIR3SEL XIR3SET XMISC XP1DIDIS XPEREMU XPICON XPOLAR XPP0 XPP1 XPP2 XPP3 XPT0 XPT1
ST10F276Z5 X-Registers ordered by name (continued)
Physical address ED10h ED0Eh ED08h ED06h EB02h EB76h EB78h EB7Ah EB7Ch EB14h EB10h EB12h EB24h EB20h EB22h EB34h EB30h EB32h EB44h EB40h EB42h EB46h EB36h EB7Eh EB26h EC04h EC20h EC22h EC24h EC26h EC10h EC12h Description RTC Programmable counter high byte RTC Programmable counter low byte RTC Prescaler register high byte RTC Prescaler register low byte CLKOUT Divider control register XBUS Emulation register 0 (write-only) XBUS Emulation register 1 (write-only) XBUS Emulation register 2 (write-only) XBUS Emulation register 3 (write-only) X-Interrupt 0 clear register (write-only) X-Interrupt 0 selection register X-Interrupt 0 set register (write-only) X-Interrupt 1 clear register (write-only) X-Interrupt 1 selection register X-Interrupt 1 set register (write-only) X-Interrupt 2 clear register (write-only) X-Interrupt 2 selection register X-Interrupt 2 set register (write-only) X-Interrupt 3 clear selection register (writeonly) X-Interrupt 3 selection register X-Interrupt 3 set selection register (writeonly) XBUS miscellaneous features register Port 1 digital disable register XPERCON copy for emulation (write-only) Extended port input threshold control register XPWM module channel polarity register XPWM module period register 0 XPWM module period register 1 XPWM module period register 2 XPWM module period register 3 XPWM module up/down counter 0 XPWM module up/down counter 1 Reset value XXXXh XXXXh XXXXh XXXXh - - 00h XXXXh XXXXh XXXXh XXXXh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXXXh - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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ST10F276Z5 Table 70.
Name XPT2 XPT3 XPW0 XPW1 XPW2 XPW3 XPWMCON0 XPWMCON0CLR XPWMCON0SET XPWMCON1 XPWMCON1CLR XPWMCON1SET XPWMPORT XS1BG XS1CON XS1CONCLR XS1CONSET XS1PORT XS1RBUF XS1TBUF XSSCBR XSSCCON XSSCCONCLR XSSCCONSET XSSCPORT XSSCRB XSSCTB
Register set X-Registers ordered by name (continued)
Physical address EC14h EC16h EC30h EC32h EC34h EC36h EC00h EC08h EC06h EC02h EC0Ch EC0Ah EC80h E906h E900h E904h E902h E980h E90Ah E908h E80Ah E800h E804h E802h E880h E808h E806h Description XPWM module up/down counter 2 XPWM module up/down counter 3 XPWM module pulse width register 0 XPWM module pulse width register 1 XPWM module pulse width register 2 XPWM module pulse width register 3 XPWM module control register 0 XPWM module clear control reg. 0 (writeonly) XPWM module set control register 0 (writeonly) XPWM module control register 1 XPWM module clear control reg. 0 (writeonly) XPWM module set control register 0 (writeonly) XPWM module port control register XASC baud rate generator reload register XASC control register XASC clear control register (write-only) XASC set control register (write-only) XASC port control register XASC receive buffer register XASC transmit buffer register XSSC baud rate register XSSC control register XSSC clear control register (write-only) XSSC set control register (write-only) XSSC port control register XSSC receive buffer XSSC transmit buffer Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXXXh 0000h
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Register set
ST10F276Z5
22.6
X-registers ordered by address
The following table lists by order of their physical addresses all X-Bus registers which are implemented in the ST10F276Z5. Although also physically mapped on X-Bus memory space, the Flash control registers are listed in a separate section, .
Note:
The X-registers are not bit-addressable. Table 71.
Name XSSCCON XSSCCONSET XSSCCONCLR XSSCTB XSSCRB XSSCBR XSSCPORT XS1CON XS1CONSET XS1CONCLR XS1BG XS1TBUF XS1RBUF XS1PORT I2CCR I2CSR1 I2CSR2 I2CCCR1 I2COAR1 I2COAR2 I2CDR I2CCCR2 XCLKOUTDIV XIR0SEL XIR0SET XIR0CLR XIR1SEL XIR1SET XIR1CLR
X-registers ordered by address
Physical address E800h E802h E804h E806h E808h E80Ah E880h E900h E902h E904h E906h E908h E90Ah E980h EA00h EA02h EA04h EA06h EA08h EA0Ah EA0Ch EA0Eh EB02h EB10h EB12h EB14h EB20h EB22h EB24h Description XSSC control register XSSC set control register (write-only) XSSC clear control register (write-only) XSSC transmit buffer XSSC receive buffer XSSC baud rate register XSSC port control register XASC control register XASC set control register (write-only) XASC clear control register (write-only) XASC baud rate generator reload register XASC transmit buffer register XASC receive buffer register XASC port control register I2C control register I2C status register 1 I2C status register 2 I2C clock control register 1 I2C own address register 1 I2C own address register 2 I2C data register I2C clock control register 2 CLKOUT divider control register X-Interrupt 0 selection register X-Interrupt 0 set register (write-only) X-Interrupt 0 clear register (write-only) X-Interrupt 1 selection register X-Interrupt 1 set register (write-only) X-Interrupt 1 clear register (write-only) Reset value 0000h 0000h 0000h 0000h XXXXh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h - - 00h 0000h 0000h 0000h 0000h 0000h 0000h
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ST10F276Z5 Table 71.
Name XPICON XIR2SEL XIR2SET XIR2CLR XP1DIDIS XIR3SEL XIR3SET XIR3CLR XMISC XEMU0 XEMU1 XEMU2 XEMU3 XPEREMU XPWMCON0 XPWMCON1 XPOLAR XPWMCON0SET XPWMCON0CLR XPWMCON1SET XPWMCON1CLR XPT0 XPT1 XPT2 XPT3 XPP0 XPP1 XPP2 XPP3 XPW0
Register set X-registers ordered by address (continued)
Physical address EB26h EB30h EB32h EB34h EB36h EB40h EB42h EB44h EB46h EB76h EB78h EB7Ah EB7Ch EB7Eh EC00h EC02h EC04h EC06h EC08h EC0Ah EC0Ch EC10h EC12h EC14h EC16h EC20h EC22h EC24h EC26h EC30h Description Extended port input threshold control register X-Interrupt 2 selection register X-Interrupt 2 set register (write-only) X-Interrupt 2 clear register (write-only) Port 1 digital disable register X-Interrupt 3 selection register X-Interrupt 3 set selection register (write-only) X-Interrupt 3 clear selection register (write-only) XBUS miscellaneous features register XBUS emulation register 0 (write-only) XBUS emulation register 1 (write-only) XBUS emulation register 2 (write-only) XBUS emulation register 3 (write-only) XPERCON copy for emulation (write-only) XPWM module control register 0 XPWM module control register 1 XPWM module channel polarity register XPWM module set control register 0 (write-only) XPWM module clear control reg. 0 (write-only) XPWM module set control register 0 (write-only) XPWM module clear control reg. 0 (write-only) XPWM module up/down counter 0 XPWM module up/down counter 1 XPWM module up/down Counter 2 XPWM module up/down counter 3 XPWM module period register 0 XPWM module period register 1 XPWM module period register 2 XPWM module period register 3 XPWM module pulse width register 0 Reset value - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXXXh XXXXh XXXXh XXXXh XXXXh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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Register set Table 71.
Name XPW1 XPW2 XPW3 XPWMPORT RTCCON RTCPL RTCPH RTCDL RTCDH RTCL RTCH RTCAL RTCAH CAN2CR CAN2SR CAN2EC CAN2BTR CAN2IR CAN2TR CAN2BRPER CAN2IF1CR CAN2IF1CM CAN2IF1M1 CAN2IF1M2 CAN2IF1A1 CAN2IF1A2 CAN2IF1MC CAN2IF1DA1 CAN2IF1DA2 CAN2IF1DB1 CAN2IF1DB2 CAN2IF2CR CAN2IF2CM CAN2IF2M1
ST10F276Z5 X-registers ordered by address (continued)
Physical address EC32h EC34h EC36h EC80h ED00H ED06h ED08h ED0Ah ED0Ch ED0Eh ED10h ED12h ED14h EE00h EE02h EE04h EE06h EE08h EE0Ah EE0Ch EE10h EE12h EE14h EE16h EE18h EE1Ah EE1Ch EE1Eh EE20h EE22h EE24h EE40h EE42h EE44h Description XPWM module pulse width register 1 XPWM module pulse width register 2 XPWM module pulse width register 3 XPWM module port control register RTC control register RTC prescaler register low byte RTC prescaler register high byte RTC divider counter low byte RTC divider counter high byte RTC programmable counter low byte RTC programmable counter high byte RTC alarm register low byte RTC alarm register high byte CAN2: CAN control register CAN2: status register CAN2: error counter CAN2: bit timing register CAN2: interrupt register CAN2: test register CAN2: BRP extension register CAN2: IF1 command request CAN2: IF1 command mask CAN2: IF1 mask 1 CAN2: IF1 mask 2 CAN2: IF1 arbitration 1 CAN2: IF1 arbitration 2 CAN2: IF1 message control CAN2: IF1 data A 1 CAN2: IF1 data A 2 CAN2: IF1 data B 1 CAN2: IF1 data B 2 CAN2: IF2 command request CAN2: IF2 command mask CAN2: IF2 mask 1 Reset value 0000h 0000h 0000h 0000h 000Xh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh 0001h 0000h 0000h 2301h 0000h 00x0h 0000h 0001h 0000h FFFFh FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0001h 0000h FFFFh
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ST10F276Z5 Table 71.
Name CAN2IF2M2 CAN2IF2A1 CAN2IF2A2 CAN2IF2MC CAN2IF2DA1 CAN2IF2DA2 CAN2IF2DB1 CAN2IF2DB2 CAN2TR1 CAN2TR2 CAN2ND1 CAN2ND2 CAN2IP1 CAN2IP2 CAN2MV1 CAN2MV2 CAN1CR CAN1SR CAN1EC CAN1BTR CAN1IR CAN1TR CAN1BRPER CAN1IF1CR CAN1IF1CM CAN1IF1M1 CAN1IF1M2 CAN1IF1A1 CAN1IF1A2 CAN1IF1MC CAN1IF1DA1 CAN1IF1DA2 CAN1IF1DB1 CAN1IF1DB2
Register set X-registers ordered by address (continued)
Physical address EE46h EE48h EE4Ah EE4Ch EE4Eh EE50h EE52h EE54h EE80h EE82h EE90h EE92h EEA0h EEA2h EEB0h EEB2h EF00h EF02h EF04h EF06h EF08h EF0Ah EF0Ch EF10h EF12h EF14h EF16h EF18h EF1Ah EF1Ch EF1Eh EF20h EF22h EF24h Description CAN2: IF2 mask 2 CAN2: IF2 arbitration 1 CAN2: IF2 arbitration 2 CAN2: IF2 message control CAN2: IF2 data A 1 CAN2: IF2 data A 2 CAN2: IF2 data B 1 CAN2: IF2 data B 2 CAN2: transmission request 1 CAN2: transmission request 2 CAN2: new data 1 CAN2: new data 2 CAN2: interrupt pending 1 CAN2: interrupt pending 2 CAN2: message valid 1 CAN2: message valid 2 CAN1: CAN control register CAN1: status register CAN1: error counter CAN1: bit timing register CAN1: interrupt register CAN1: test register CAN1: BRP extension register CAN1: IF1 command request CAN1: IF1 command mask CAN1: IF1 mask 1 CAN1: IF1 mask 2 CAN1: IF1 arbitration 1 CAN1: IF1 arbitration 2 CAN1: IF1 message control CAN1: IF1 data A 1 CAN1: IF1 data A 2 CAN1: IF1 data B 1 CAN1: IF1 data B 2 Reset value FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0001h 0000h 0000h 2301h 0000h 00x0h 0000h 0001h 0000h FFFFh FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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Register set Table 71.
Name CAN1IF2CR CAN1IF2CM CAN1IF2M1 CAN1IF2M2 CAN1IF2A1 CAN1IF2A2 CAN1IF2MC CAN1IF2DA1 CAN1IF2DA2 CAN1IF2DB1 CAN1IF2DB2 CAN1TR1 CAN1TR2 CAN1ND1 CAN1ND2 CAN1IP1 CAN1IP2 CAN1MV1 CAN1MV2
ST10F276Z5 X-registers ordered by address (continued)
Physical address EF40h EF42h EF44h EF46h EF48h EF4Ah EF4Ch EF4Eh EF50h EF52h EF54h EF80h EF82h EF90h EF92h EFA0h EFA2h EFB0h EFB2h Description CAN1: IF2 command request CAN1: IF2 command mask CAN1: IF2 mask 1 CAN1: IF2 mask 2 CAN1: IF2 arbitration 1 CAN1: IF2 arbitration 2 CAN1: IF2 message control CAN1: IF2 data A 1 CAN1: IF2 data A 2 CAN1: IF2 data B 1 CAN1: IF2 data B 2 CAN1: transmission request 1 CAN1: transmission request 2 CAN1: new data 1 CAN1: new data 2 CAN1: interrupt pending 1 CAN1: interrupt pending 2 CAN1: message valid 1 CAN1: message valid 2 Reset value 0001h 0000h FFFFh FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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ST10F276Z5
Register set
22.7
Flash registers ordered by name
The following table lists by order of their names all FLASH control registers which are implemented in the ST10F276Z5. Note that as they are physically mapped on the X-Bus, these registers are not bit-addressable. Table 72.
Name FARH FARL FCR0H FCR0L FCR1H FCR1L FDR0H FDR0L FDR1H FDR1L FER FNVAPR0 FNVAPR1H FNVAPR1L FNVWPIRH FNVWPIRL FNVWPXRH FNVWPXRL XFICR
Flash registers ordered by name
Physical address 0x000E 0012 0x000E 0010 0x000E 0002 0x000E 0000 0x000E 0006 0x000E 0004 0x000E 000A 0x000E 0008 0x000E 000E 0x000E 000C 0x000E 0014 0x000E DFB8 0x000E DFBE 0x000E DFBC 0x000E DFB6 0x000E DFB4 0x000E DFB2 0x000E DFB0 0x000E E000 Description Flash address register High Flash address register Low Flash control register 0 - High Flash control register 0 - Low Flash control register 1 - High Flash control register 1 - Low Flash data register 0 - High Flash data register 0 - Low Flash data register 1 - High Flash data register 1 - Low Flash error register Flash nonvolatile access protection Reg. 0 Flash nonvolatile access protection Reg. 1 - High Flash nonvolatile access protection Reg. 1 - Low Flash nonvolatile protection I Reg. High Flash nonvolatile protection I Reg. Low Flash nonvolatile protection X Reg. High Flash nonvolatile protection X Reg. Low XFlash interface control register Reset value 0000h 0000h 0000h 0000h 0000h 0000h FFFFh FFFFh FFFFh FFFFh 0000h ACFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh 000Fh
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Register set
ST10F276Z5
22.8
Flash registers ordered by address
The following table lists by order of their physical addresses all FLASH control registers which are implemented in the ST10F276Z5. Note that as they are physically mapped on the X-Bus, these registers are not bit-addressable. Table 73.
Name FCR0L FCR0H FCR1L FCR1H FDR0L FDR0H FDR1L FDR1H FARL FARH FER FNVWPXRL FNVWPXRH FNVWPIRL FNVWPIRH FNVAPR0 FNVAPR1L FNVAPR1H XFICR
FLASH registers ordered by address
Physical address 0x000E 0000 0x000E 0002 0x000E 0004 0x000E 0006 0x000E 0008 0x000E 000A 0x000E 000C 0x000E 000E 0x000E 0010 0x000E 0012 0x000E 0014 0x000E DFB0 0x000E DFB2 0x000E DFB4 0x000E DFB6 0x000E DFB8 0x000E DFBC 0x000E DFBE 0x000E E000 Description Flash control register 0 - Low Flash control register 0 - High Flash control register 1 - Low Flash control register 1 - High Flash data register 0 - Low Flash data register 0 - High Flash data register 1 - Low Flash data register 1 - High Flash address register Low Flash address register High Flash error register Flash nonvolatile protection X reg. Low Flash nonvolatile protection X reg. High Flash nonvolatile protection I reg. Low Flash nonvolatile protection I reg. High Flash nonvolatile access protection reg. 0 Flash nonvolatile access protection reg. 1 Low Flash nonvolatile access protection reg. 1 High XFlash interface control register Reset value 0000h 0000h 0000h 0000h FFFFh FFFFh FFFFh FFFFh 0000h 0000h 0000h FFFFh FFFFh FFFFh FFFFh ACFFh FFFFh FFFFh 000Fh
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ST10F276Z5
Register set
22.9
Identification registers
The ST10F276Z5 has four Identification registers, mapped in ESFR space. These registers contain:

The manufacturer identifier The chip identifier with revision number The internal Flash and size identifier the programming voltage description
ESFR 11 10 MANUF R 9 8 7 6 5 4 0 3 0 Reset value:0403h 2 0 1 1 0 1
IDMANUF (F07Eh / 3Fh) 15 14 13 12
Table 74.
Bit MANUF
MANUF description
Function Manufacturer identifier 020h: STMicroelectronics manufacturer (JTAG worldwide normalization) ESFR 11 10 R 9 8 7 6 5 4 3 IDCHIP Reset value:114xh 2 R 1 0 REVID
IDCHIP (F07Ch / 3Eh) 15 14 13 12
Table 75.
Bit IDCHIP REVID
IDCHIP description
Function Device identifier 114h: ST10F276Z5 Identifier (276) Device revision identifier Xh: According to revision number ESFR 11 10 9 8 7 6 R 5 4 3 MEMSIZE Reset value:30D0h 2 1 0
IDMEM (F07Ah / 3Dh) 15 14 R 13 12 MEMTYP
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Register set Table 76.
Bit
ST10F276Z5 IDMEM description
Function Internal memory size Internal Memory size is 4 x (MEMSIZE) (in Kbyte) 0D0h for ST10F276Z5 (832 Kbytes) Internal memory type `0h': ROM-Less `1h': (M) ROM memory `2h': (S) Standard FLASH memory `3h': (H) High Performance FLASH memory (ST10F276Z5) `4h...Fh': reserved ESFR 11 R 10 9 8 7 6 5 4 R 3 PROGVDD Reset value:0040h 2 1 0
MEMSIZE
MEMTYP
IDPROG (F078h / 3Ch) 15 14 13 12 PROGVPP
Table 77.
Bit
IDPROG description
Function Programming VDD voltage VDD voltage when programming EPROM or FLASH devices is calculated using the following formula: VDD = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F276Z5 (5 V). Programming VPP voltage (no need of external VPP) - 00h
PROGVDD
PROGVPP
Note:
All identification words are read-only registers. The values written inside different Identification Register bits are valid only after the Flash initialization phase is completed. When code execution is started from internal memory (pin EA held high during reset), the Flash has completed its initialization, so the bits of Identification Registers are immediately ready to be read out. On the contrary, when code execution is started from external memory (pin EA held low during reset), the Flash initialization is not yet completed, so the bits of Identification Registers are not ready. The user can poll bits 15 and 14 of IDMEM register: When both bits are read low, the Flash initialization is complete, so all Identification Register bits are correct. Before Flash initialization completion, the default setting of the different identification registers are the following: Table 78. Identification register settings
Value
Register name
IDMANUF IDCHIP IDMEM IDPROG
0403h 114xh (x = silicon revision) F0D0h 0040h
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ST10F276Z5
Register set
22.10
System configuration registers
The ST10F276Z5 registers are used for a different configuration of the overall system. These registers are described below.
SYSCON (FF12h / 89h) 15 14
STKSZ
SFR 11 10
ROM EN
Reset value: 0xx0h 7
WR CFG
13
12
ROM S1
9
BYT DIS
8
CLK EN
6
CS CFG
5
PWD CFG
4
OWD DIS
3
BDR STEN
2
XPEN
1
VISI BLE
0
XPERSHARE
SGT DIS
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Note:
SYSCON Reset Value is: 0000 0xx0 0x00 0000b Table 79.
Bit
.
SYSCON description
Function XBUS peripheral share mode control `0': External accesses to XBUS peripherals are disabled. `1': XRAM1 and XRAM2 are accessible via the external bus during hold mode. External accesses to the other XBUS peripherals are not guaranteed in terms of AC timings. Visible mode control `0': Accesses to XBUS peripherals are done internally. `1': XBUS peripheral accesses are made visible on the external pins. XBUS peripheral enable bit `0': Accesses to the on-chip X-peripherals and XRAM are disabled. `1': The on-chip X-peripherals are enabled. Bidirectional reset enable `0': RSTIN pin is an input pin only. SW Reset or WDT Reset have no effect on this pin. `1': RSTIN pin is a bidirectional pin. This pin is pulled low during internal reset sequence. Oscillator watchdog disable control `0': Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activity. If there is no activity on XTAL1 for at least 1 s, the CPU clock is switched automatically to PLL's base frequency (from 750 kHz to 3 MHz). `1': OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The PLL is turned off to reduce power supply current. Power-down mode configuration control `0': Power-down mode can only be entered during PWRDN instruction execution if NMI pin is low, otherwise the instruction has no effect. To exit Power-down mode, an external reset must occur by asserting the RSTIN pin. `1': Power-down mode can only be entered during PWRDN instruction execution if all enabled fast external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting one enabled EXxIN pin or with external reset. Chip select configuration control `0': Latched Chip Select lines, CSx changes 1 TCL after rising edge of ALE. `1': Unlatched Chip Select lines, CSx changes with rising edge of ALE.
XPER-SHARE
VISIBLE
XPEN
BDRSTEN
OWDDIS
PWDCFG
CSCFG
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Register set Table 79.
Bit
ST10F276Z5 SYSCON description (continued)
Function Write configuration control (inverted copy of WRC bit of RP0H) `0': Pins WR and BHE retain their normal function. `1': Pin WR acts as WRL, pin BHE acts as WRH. System clock output enable (CLKOUT) `0': CLKOUT disabled, pin may be used for general purpose I/O. `1': CLKOUT enabled, pin outputs the system clock signal or a prescaled value of system clock according to XCLKOUTDIV register setting. Disable/enable control for pin BHE (set according to data bus width) `0': Pin BHE enabled. `1': Pin BHE disabled, pin may be used for general purpose I/O. Internal memory enable (set according to pin EA during reset) `0': Internal memory disabled: Accesses to the IFlash Memory area use the external bus. `1': Internal memory enabled. Segmentation disable/enable control `0': Segmentation enabled (CSP is saved/restored during interrupt entry/exit). `1': Segmentation disabled (Only IP is saved/restored). Internal memory mapping `0': Internal memory area mapped to segment 0 (00'0000h...00'7FFFh). `1': Internal memory area mapped to segment 1 (01'0000h...01'7FFFh). System stack size Selects the size of the system stack (in the internal I-RAM) from 32 to 1024 words. SFR 12 RW 11
-
WRCFG
CLKEN
BYTDIS
ROMEN
SGTDIS
ROMS1
STKSZ
BUSCON0 (FF0Ch / 86h) 15 RW 14 RW 13 10 RW 9 RW
CSWEN0 CSREN0 RDYPOL0 RDYEN0
Reset value: 0xx0h 7
BTYP
8
-
6 RW
5 RW
4 RW
3
2
1
0
BUSACT0 ALECTL0
MTTC0 RWDC0
MCTC
RW
BUSCON1 (FF14h / 8Ah) 15 RW 14 RW 13 RW 12 RW 11
-
SFR 10 RW 9 RW SFR 12 RW 11
-
Reset value: 0000h 7
BTYP
8
-
6 RW
5 RW
4 RW
3
2
1
0
CSWEN1 CSREN1 RDYPOL1 RDYEN1
BUSACT1 ALECTL1
MTTC1 RWDC1
MCTC
RW
BUSCON2 (FF16h / 8Bh) 15 RW 14 RW 13 10 RW 9 RW
CSWEN2 CSREN2 RDYPOL2 RDYEN2
Reset value: 0000h 7
BTYP
8
-
6 RW
5 RW
4 RW
3
2
1
0
BUSACT2 ALECTL2
MTTC2 RWDC2
MCTC
RW
BUSCON3 (FF18h / 8Ch) 15 RW 14 RW 13 12 RW 11
-
SFR 10 RW 9 RW 8
-
Reset value: 0000h 7
BTYP
6 RW
5 RW
4 RW
3
2
1
0
CSWEN3 CSREN3 RDYPOL3 RDYEN3
BUSACT3 ALECTL3
MTTC3 RWDC3
MCTC
RW
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ST10F276Z5
Register set
BUSCON4 (FF1Ah / 8Dh) 15 RW 14 RW 13 12 RW 11
-
SFR 10 RW 9 RW 8
-
Reset value: 0000h 7
BTYP
6 RW
5 RW
4 RW
3
2
1
0
CSWEN4 CSREN4 RDYPOL4 RDYEN4
BUSACT4 ALECTL4
MTTC4 RWDC4
MCTC
RW
Table 80.
Bit
BUSCON4 description
Function Memory cycle time control (number of memory cycle time wait-states) '0000': 15 wait-states (Number of wait-states = 15 - [MCTC]). ... '1111': No wait-states. Read/Write delay control for BUSCONx `0': With read/write delay, the CPU inserts 1 TCL after falling edge of ALE. `1': No read/write delay, RW is activated after falling edge of ALE. Memory tri-state time control `0': 1 wait-state. `1': No wait-state. External bus configuration '00': 8-bit Demultiplexed Bus '01': 8-bit Multiplexed Bus '10': 16-bit Demultiplexed Bus '11': 16-bit Multiplexed Bus Note: For BUSCON0 BTYP is defined via PORT0 during reset. ALE lengthening control `0': Normal ALE signal. `1': Lengthened ALE signal. Bus active control `0': External bus disabled. `1': External bus enabled (within the respective address window, see ADDRSEL). Ready input enable `0': External bus cycle is controlled by bit field MCTC only. `1': External bus cycle is controlled by the READY input signal. Ready active level control `0': Active level on the READY pin is low, bus cycle terminates with a `0' on READY pin. `1': Active level on the READY pin is high, bus cycle terminates with a `1' on READY pin. Read chip select enable `0': The CS signal is independent of the read command (RD). `1': The CS signal is generated for the duration of the read command. Write chip select enable `0': The CS signal is independent of the write command (WR, WRL, WRH). `1': The CS signal is generated for the duration of the write command.
MCTC
RWDCx
MTTCx
BTYP(1)
ALECTLx
BUSACTx
RDYENx
RDYPOLx
CSRENx
CSWENx
1. BTYP (bit 6 and 7) is set according to the configuration of the bit l6 and l7 of PORT0 latched at the end of the reset sequence.
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Register set Note:
ST10F276Z5
BUSCON0 is initialized with 0000h, if EA pin is high during reset. If EA pin is low during reset, bit BUSACT0 and ALECTRL0 are set to `1' and bit field BTYP is loaded with the bus configuration selected via PORT0.
RP0H (F108h / 84h) 15 14 13 12 11 10 9 ESFR 8 7 6 CLKSEL R 5 4 R 3 SALSEL Reset value: --XXh 2 R 1 0 WRC R CSSEL
Table 81.
Bit WRC (2)
RPOH description(1)
Function Write configuration control `0': Pin WR acts as WRL, pin BHE acts as WRH `1': Pins WR and BHE retain their normal function Chip select line selection (number of active CS outputs) 0 0: 3 CS lines: CS2...CS0 0 1: 2 CS lines: CS1...CS0 1 0: No CS line at all 1 1: 5 CS lines: CS4...CS0 (Default without pull-downs) Segment address line selection (number of active segment address outputs) '00': 4-bit segment address: A19...A16 '01': No segment address lines at all '10': 8-bit segment address: A23...A16 '11': 2-bit segment address: A17...A16 (Default without pull-downs) System clock selection '000': fCPU = 16 x fOSC '001': fCPU = 0.5 x fOSC '010': fCPU = 10 x fOSC '011': fCPU = fOSC '100': fCPU = 5 x fOSC '101': fCPU = 8 x fOSC '110': fCPU = 3 x fOSC '111': fCPU = 4 x fOSC
CSSEL (2)
SALSEL (2)
CLKSEL(2) (3)
1. RP0H is a read-only register. 2. These bits are set according to Port 0 configuration during any reset sequence. 3. RP0H.7 to RP0H.5 bits are loaded only during a long hardware reset. As pull-up resistors are active on each Port P0H pins during reset, RP0H default value is "FFh".
EXICON (F1C0h / E0h) 15 RW 14 13 RW 12 11 RW 10 9 EXI7ES EXI6ES EXI5ES
ESFR 8 RW 7 RW 6 5 RW 4 3 EXI4ES EXI3ES EXI2ES
Reset value: 0000h 2 RW 1 RW 0 EXI1ES EXI0ES
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ST10F276Z5 Table 82.
Bit
Register set EXIxES bit description
Function 00 = Fast external interrupts disabled: Standard mode. EXxIN pin not taken in account for entering/exiting Power-down mode. 01 = Interrupt on positive edge (rising). Enter Power-down mode if EXiIN = `0', exit if EXxIN = `1' (referred as "high" active level) 10 = Interrupt on negative edge (falling). Enter Power-down mode if EXiIN = `1', exit if EXxIN = `0' (referred as "low" active level) 11 = Interrupt on any edge (rising or falling). Always enter Power-down mode, exit if EXxIN level changed. ESFR 11 RW 10 9 RW 8 7 RW 6 5 RW 4 3 RW EXI5SS EXI4SS EXI3SS EXI2SS Reset value: 0000h 2 1 RW 0 EXI1SS EXI0SS
EXIxES (x=7...0)
EXISEL (F1DAh / EDh) 15 RW 14 13 RW 12 EXI7SS EXI6SS
Table 83.
Bit
EXISEL
Function External Interrupt x Source Selection (x = 7...0) 00 = Input from associated Port 2 pin. 01 = Input from "alternate source". 10 = Input from Port 2 pin ORed with "alternate source". 11 = Input from Port 2 pin ANDed with "alternate source".
EXIxSS
Table 84.
EXIxSS and port 2 pin configurations
Port 2 pin P2.8 P2.9 P2.10 P2.11 P2.12...15 ESFR 11 10 9 8 7 RW 6 RW 5 4 RW 3 Alternate source CAN1_RxD CAN2_RxD / SCL RTCSI (Second) RTCAI (Alarm) Not used (zero) Reset value: --00h 2 1
GLVL
EXIxSS 0 1 2 3 4...7 XP3IC (F19Eh / CFh) 15 14 13 12
0 RW
XP3IR XP3IE
XP3ILVL
Note:
1. XP3IC register has the same bit field as xxIC interrupt registers
xxIC (yyyyh / zzh) 15 14 13 12 11 10 9 SFR area 8 7 RW 6 RW 5 4 ILVL RW 3 xxIR xxIE Reset value: --00h 2 1 RW 0 GLVL
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Register set Table 85.
Bit
ST10F276Z5 SFR area description
Function Group level Defines the internal order for simultaneous requests of the same priority. '3': Highest group priority '0': Lowest group priority Interrupt priority level Defines the priority level for the arbitration of requests. 'Fh': Highest priority level '0h': Lowest priority level Interrupt enable control bit (individually enables/disables a specific source) `0': Interrupt request is disabled `1': Interrupt request is enabled Interrupt request flag `0': No request pending `1': This source has raised an interrupt request ESFR 11 10 9 8 7 6 5 4 3
XMISC XI2C EN EN
GLVL
ILVL
xxIE
xxIR
XPERCON (F024h / 12h) 15 14 13 12 -
Reset value:- 005h 2 1 0
XSSC XASC XPWM XFLAS XRTC XRAM2 XRAM1 CAN2 CAN1 EN EN EN HEN EN EN EN EN EN
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 86.
Bit
ESFR description
Function CAN1 enable bit `0': Accesses to the on-chip CAN1 XPeripheral and its functions are disabled (P4.5 and P4.6 pins can be used as general purpose I/Os, but address range 00'EC00h00'EFFFh is directed to external memory only if CAN2EN, XRTCEN, XASCEN, XSSCEN, XI2CEN, XPWMEN an XMISCEN are `0' also). `1': The on-chip CAN1 XPeripheral is enabled and can be accessed. CAN2 enable bit `0': Accesses to the on-chip CAN2 XPeripheral and its functions are disabled (P4.4 and P4.7 pins can be used as general purpose I/Os, but address range 00'EC00h00'EFFFh is directed to external memory only if CAN1EN, XRTCEN, XASCEN, XSSCEN, XI2CEN, XPWMEN and XMISCEN are `0' also). `1': The on-chip CAN2 XPeripheral is enabled and can be accessed. XRAM1 enable bit `0': Accesses to the on-chip 2 Kbyte XRAM are disabled. Address range 00'E000h-00'E7FFh is directed to external memory. `1': The on-chip 2 Kbyte XRAM is enabled and can be accessed. XRAM2 enable bit `0': Accesses to the on-chip 64 Kbyte XRAM are disabled, external access performed. Address range 0F'0000h-0F'FFFFh is directed to external memory only if XFLASHEN is `0' also. `1': The on-chip 64 Kbyte XRAM is enabled and can be accessed.
CAN1EN
CAN2EN
XRAM1EN
XRAM2EN
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ST10F276Z5 Table 86.
Bit
Register set ESFR description (continued)
Function RTC enable `0': Accesses to the on-chip RTC module are disabled, external access performed. Address range 00'ED00h-00'EDFF is directed to external memory only if CAN1EN, CAN2EN, XASCEN, XSSCEN, XI2CEN, XPWMEN and XMISCEN are `0' also. `1': The on-chip RTC module is enabled and can be accessed. XPWM enable `0': Accesses to the on-chip XPWM module are disabled, external access performed. Address range 00'EC00h-00'ECFF is directed to external memory only if CAN1EN, CAN2EN, XASCEN, XSSCEN, XI2CEN, XRTCEN and XMISCEN are `0' also. `1': The on-chip XPWM module is enabled and can be accessed. XFlash enable bit `0': Accesses to the on-chip XFlash and Flash registers are disabled, external access performed. Address range 09'0000h-0E'FFFFh is directed to external memory only if XRAM2EN is `0' also. `1': The on-chip XFlash is enabled and can be accessed. XASC enable bit `0': Accesses to the on-chip XASC are disabled, external access performed. Address range 00'E900h-00'E9FFh is directed to external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN, XI2CEN, XPWMEN and XMISCEN are `0' also. `1': The on-chip XASC is enabled and can be accessed. XSSC enable bit `0': Accesses to the on-chip XSSC are disabled, external access performed. Address range 00'E800h-00'E8FFh is directed to external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN, XI2CEN, XPWMEN and XMISCEN are `0' also. `1': The on-chip XSSC is enabled and can be accessed. I2C enable bit `0': Accesses to the on-chip I2C are disabled, external access performed. Address range 00'EA00h-00'EAFFh is directed to external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN, XSSCEN, XPWMEN and XMISCEN are `0' also. `1': The on-chip I2C is enabled and can be accessed. XBUS additional features enable bit `0': Accesses to the Additional Miscellaneous Features is disabled. Address range 00'EB00h-00'EBFFh is directed to external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN, XSSCEN, XPWMEN and XI2CEN are `0' also. `1': The Additional Features are enabled and can be accessed.
XRTCEN
XPWMEN
XFLASHEN
XASCEN
XSSCEN
XI2CEN
XMISCEN
When CAN1, CAN2, RTC, XASC, XSSC, I2C, XPWM and the XBUS Additional Features are all disabled via XPERCON setting, then any access in the address range 00'E800h 00'EFFFh is directed to external memory interface, using the BUSCONx register corresponding to the address matching ADDRSELx register. All pins used for X-Peripherals can be used as General Purpose I/O whenever the related module is not enabled.
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Register set
ST10F276Z5
The default XPER selection after Reset is such that CAN1 is enabled, CAN2 is disabled, XRAM1 (2 Kbyte XRAM) is enabled and XRAM2 (64 Kbyte XRAM) is disabled; all the other X-Peripherals are disabled after Reset. Register XPERCON cannot be changed after the global enabling of X-Peripherals, that is, after setting of bit XPEN in SYSCON register. In Emulation mode, all the X-Peripherals are enabled (XPERCON bits are all set). The bondout chip determines whether or not to redirect an access to external memory or to XBUS. Reserved bits of XPERCON register are always written to `0'. Table 87 below summarizes the Segment 8 mapping that depends upon the EA pin status during reset as well as the SYSCON (bit XPEN) and XPERCON (bits XRAM2EN and XFLASHEN) registers user programmed values. Table 87.
EA 0 0 0 0 1
.
Segment 8 address range mapping
XPEN 0 1 1 1 x XRAM2EN x 0 1 x x XFLASHEN x 0 x 1 x Segment 8 External memory External memory Reserved Reserved IFlash (B1F1)
Note:
The symbol "x" in the table above stands for "do not care".
22.10.1
XPERCON and XPEREMU registers
As already mentioned, the XPERCON register must be programmed to enable the single XBUS modules separately. The XPERCON is a read/write ESFR register; the XPEREMU register is a write-only register mapped on XBUS memory space (address EB7Eh). Once the XPEN bit of SYSCON register is set and at least one of the X-peripherals (except memories) is activated, the register XPEREMU must be written with the same content of XPERCON: This is mandatory in order to allow a correct emulation of the new set of features introduced on XBUS for the new ST10 generation. The following instructions must be added inside the initialization routine: if (SYSCON.XPEN && (XPERCON & 0x07D3)) then { XPEREMU = XPERCON } Of course, XPEREMU must be programmed after XPERCON and after SYSCON; in this way the final configuration for X-Peripherals is stored in XPEREMU and used for the emulation hardware setup.
XPEREMU (EB7Eh) 15 14 13 12 11 10 9
XMISC XI2C EN EN
XBUS 8 7 6 5 4 3
Reset value xxxxh: 2 1 0
XSSC XASC XPWM XFLAS XRTC XRAM2 XRAM1 CAN2 CAN1 EN EN EN HEN EN EN EN EN EN
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Note:
The bit meaning is exactly the same as in XPERCON.
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ST10F276Z5
Register set
22.11
Emulation dedicated registers
Four additional registers are implemented for emulation purposes only. Similarly to XPEREMU, they are write-only registers.
XEMU0 (EB76h) 15 14 13 12 11 10 9 XBUS 8 W XEMU1 (EB78h) 15 14 13 12 11 10 9 XBUS 8 W XEMU2 (EB7Ah) 15 14 13 12 11 10 9 XBUS 8 W XEMU3 (EB7Ch) 15 14 13 12 11 10 9 XBUS 8 W 7 6 5 4 3 XEMU3(15:0) Reset value: xxxxh 2 1 0 7 6 5 4 3 XEMU2(15:0) Reset value: xxxxh: 2 1 0 7 6 5 4 3 XEMU1(15:0) Reset value: xxxxh 2 1 0 7 6 5 4 3 XEMU0(15:0) Reset value: xxxxh 2 1 0
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Electrical characteristics
ST10F276Z5
23
23.1
Electrical characteristics
Absolute maximum ratings
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS) the voltage on pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. During Power-on and Power-off transients (including Standby entering/exiting phases), the relationships between voltages applied to the device and the main VDD must always be respected. In particular, power-on and power-off of VAREF must be coherent with the VDD transient, in order to avoid undesired current injection through the on-chip protection diodes. Table 88.
Symbol
VDD VSTBY VAREF VAGND VIO IOV ITOV TST ESD
Absolute maximum ratings
Parameter
Voltage on VDD pins with respect to ground (VSS) Voltage on VSTBY pin with respect to ground (VSS) Voltage on VAREF pin with respect to ground (VSS) Voltage on VAGND pin with respect to ground (VSS) Voltage on any pin with respect to ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Storage temperature ESD susceptibility (human body model) - 0.3 to VDD + 0.3 VSS - 0.5 to VDD + 0.5 10 | 75 | - 65 to +150 2000 mA C V V
Value
- 0.3 to +6.5
Unit
23.2
Recommended operating conditions
Table 89.
Symbol
VDD VSTBY VAREF TA TJ
Recommended operating conditions
Parameter
Operating supply voltage Operating standby supply voltage(1) Operating analog reference voltage Ambient temperature under bias -40 Junction temperature under bias +150
(2)
Min.
4.5 0
Max.
5.5
Unit
V VDD +125 C
1. The value of the VSTBY voltage is specified in the range 4.5 - 5.5 V. Nevertheless, it is acceptable to exceed the upper limit (up to 6.0 V) for a maximum of 100 hrs over the global 300000 hrs, representing the lifetime of the device (about 30 years). On the other hand, it is possible to exceed the lower limit (down to 4.0 V) whenever RTC and 32 kHz on-chip oscillator amplifier are turned off (only Standby RAM powered through VSTBY pin in Standby mode). When VSTBY voltage is lower than main VDD, the input section of VSTBY/EA pin can generate a spurious static consumption on VDD power supply (in the range of tenth of 1 mA). 2. For details on operating conditions concerning the usage of A/D converter, refer to Section 23.7.
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ST10F276Z5
Electrical characteristics
23.3
Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, is calculated using the following equation: TJ = TA + (PD x JA) 1) Where: TA is the Ambient Temperature in C, JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, PD is the sum of PINT and PI/O (PD = PINT + PI/O), PINT is the product of IDD and VDD, expressed in Watt. This is the Chip Internal Power, PI/O represents the Power Dissipation on Input and Output Pins; user determined. Most often in applications, PI/O < PINT,which may be ignored. On the other hand, PI/O may be significant if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273 C) (2) Therefore (solving equations 1 and 2): K = PD x (TA + 273 C) + JA x PD2 (3) Where: K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ are obtained by solving equations (1) and (2) iteratively for any value of TA. Table 90.
Symbol
Thermal characteristics
Description Thermal resistance junction-ambient PQFP 144 - 28 x 28 x 3.4 mm / 0.65 mm pitch LQFP 144 - 20 x 20 mm / 0.5 mm pitch LQFP 144 - 20 x 20 mm / 0.5 mm pitch on four layer FR4 board (2 layers signals / 2 layers power) Value (typical) Unit
JA
30 40 35
C/W
Based on thermal characteristics of the package and with reference to the power consumption figures provided in the next tables and diagrams, the following product classification can be proposed. In any case, the exact power consumption of the device inside the application must be computed according to different working conditions, thermal profiles, real thermal resistance of the system (including printed circuit board or other substrata) and I/O activity.
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Electrical characteristics Table 91. Package characteristics
Package Die PQFP 144 LQFP 144 LQFP 144 -40/+105 C - 40 / +125 C Operating temperature
ST10F276Z5
CPU frequency range 1 - 64 MHz 1 - 40 MHz 1 - 48 MHz
23.4
Parameter interpretation
The parameters listed in the following tables represent the characteristics of the ST10F276Z5 and its demands on the system. Where the ST10F276Z5 logic provides signals with their respective timing characteristics, the symbol "CC" (Controller Characteristics) is included in the "Symbol" column. Where the external system must provide signals with their respective timing characteristics to the device, the symbol "SR" (System Requirement) is included in the "Symbol" column.
23.5
DC characteristics
VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C. Table 92.
Symbol
DC characteristics
Limit values Parameter Input low voltage (TTL mode) (except RSTIN, EA, NMI, RPD, XTAL1, READY) Input low voltage (CMOS mode) (except RSTIN, EA, NMI, RPD, XTAL1, READY) Input low voltage RSTIN, EA, NMI, RPD Input low voltage XTAL1 (CMOS only) Input low voltage READY (TTL only) Test Condition Min. Max. 0.8 Unit
VIL
SR
-
- 0.3
VILS
SR
-
- 0.3
0.3 VDD V
VIL1 VIL2 VIL3
SR SR SR
- Direct drive mode -
- 0.3 - 0.3 - 0.3
0.3 VDD 0.3 VDD 0.8
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ST10F276Z5 Table 92.
Symbol
Electrical characteristics DC characteristics (continued)
Limit values Parameter Input high voltage (TTL mode) (except RSTIN, EA, NMI, RPD, XTAL1) Input high voltage (CMOS mode) (except RSTIN, EA, NMI, RPD, XTAL1) Input high voltage RSTIN, EA, NMI, RPD Input high voltage XTAL1 (CMOS only) Input high voltage READY (TTL only) Input hysteresis (TTL mode) (except RSTIN, EA, NMI, XTAL1, RPD) Test Condition Min. VIH SR - 2.0 Max. VDD + 0.3 Unit
VIHS
SR
-
0.7 VDD
VDD + 0.3 V
VIH1 VIH2 VIH3
SR SR SR
- Direct Drive mode -
0.7 VDD 0.7 VDD 2.0
VDD + 0.3 VDD + 0.3 VDD + 0.3
VHYS CC
(3)
400
700
Input Hysteresis (CMOS mode) VHYSSCC (except RSTIN, EA, NMI, XTAL1, RPD) VHYS1CC Input hysteresis RSTIN, EA, NMI VHYS2CC Input hysteresis XTAL1 VHYS3CC Input hysteresis READY (TTL only) VHYS4CC Input hysteresis RPD Output low voltage (P6[7:0], ALE, RD, WR/WRL, BHE/WRH, CLKOUT, RSTIN, RSTOUT) Output low voltage (P0[15:0], P1[15:0], P2[15:0], P3[15,13:0], P4[7:0], P7[7:0], P8[7:0]) Output low voltage RPD Output high voltage (P6[7:0], ALE, RD, WR/WRL, BHE/WRH, CLKOUT, RSTOUT) Output high voltage(1) (P0[15:0], P1[15:0], P2[15:0], P3[15,13:0], P4[7:0], P7[7:0], P8[7:0]) Output high voltage RPD
(3)
750 750 0 400 500
1400 mV 1400 50 700 1500 0.4 0.05
(3) (3) (3) (3)
VOL
CC
IOL = 8 mA IOL = 1 mA
-
VOL1
CC
IOL1 = 4 mA IOL1 = 0.5 mA IOL2 = 85 A IOL2 = 80 A IOL2 = 60 A IOH = - 8 mA IOH = - 1 mA
-
0.4 0.05 VDD 0.5 VDD 0.3 VDD -
VOL2
CC
-
V
VOH
CC
VDD - 0.8 VDD - 0.08
VOH1 CC
IOH1 = - 4 mA VDD - 0.8 IOH1 = - 0.5 mA VDD - 0.08 IOH2 = - 2 mA IOH2 = - 750 A IOH2 = - 150 A 0 0.3 VDD 0.5 VDD
-
VOH2 CC
-
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Electrical characteristics Table 92.
Symbol
|IOZ1 | CC |IOZ2 | CC |IOZ3 | CC |IOZ4 | CC |IOV1 | SR |IOV2 | SR
ST10F276Z5
DC characteristics (continued)
Limit values Parameter Input leakage current (P5[15:0]) (2) Input leakage current (all except P5[15:0], P2.0, RPD) Input leakage current (P2.0) (3) Input leakage current (RPD) Overload current (all except P2.0) Overload current (P2.0) (3) RSTIN pull-up resistor Read/Write inactive current (6) (7) Read/Write active current ALE inactive current ALE active current
(6) (7) (6)(8) (4) (5) (4)(5)
Test Condition Min. - - - - - - - - - - 50 - -500 20 - - -500 - -100 - - - - TA = 25 C - - - - Max. 0.2 0.5
Unit
A +1.0 -0.5 3.0 5 +5 -1 250 -40 - - 300 A VOUT = 2.4 V -40 - -10 - 10 20 + 2 fCPU
20 + 1.8 fCPU 20 + 0.6 fCPU
mA mA k
RRST CC IRWH IRWL IALEL IALEH IP6H IP6L IP0H IP0L CIO ICC1 ICC2 IID IPD1
6) 7)
100 k nominal VOUT = 2.4 V VOUT = 0.4 V VOUT = 0.4 V VOUT = 2.4 V
(6) (8)
Port 6 inactive current (P6[4:0])(6)(7)
Port 6 active current (P6[4:0])(6) (8) VOUT = 0.4 V PORT0 configuration current (6) Pin capacitance (digital inputs / outputs) Run mode power supply current(9) (execution from internal RAM) Run mode power supply current (4)(9)(execution from internal Flash) Idle mode supply current (10) Power-down supply current (11) (RTC off, oscillators off, main voltage regulator off) Power-down supply current (11) (RTC on, main oscillator on, main voltage regulator off) Power-down supply current (11) (RTC on, 32 kHz oscillator on, main voltage regulator off) Standby supply current (11) (RTC off, Oscillators off, VDD off, VSTBY on) VIN = 2.0 V VIN = 0.8 V CC
(4)(6)
pF mA mA mA mA
1
IPD2
TA = 25 C
-
8
mA
IPD3
TA = 25 C VSTBY = 5.5 V TA = TJ = 25 C VSTBY = 5.5 V TA = TJ = 125 C
-
1.1
mA
- -
250 500
A A
ISB1
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ST10F276Z5 Table 92.
Symbol
Electrical characteristics DC characteristics (continued)
Limit values Parameter Test Condition Min. Standby supply current (11) (RTC on, 32 kHz Oscillator on, main VDD off, VSTBY on) Standby supply current (4) (11) (VDD transient condition) VSTBY = 5.5 V TA = 25 C VSTBY = 5.5 V TA = 125 C - - - - Max. 250 500 2.5 A A mA Unit
ISB2
ISB3
1. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output floats and the voltage is imposed by the external circuitry. 2. Port 5 leakage values are granted for not selected A/D converter channel. One channels is always selected (by default, after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins. 3. The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes) implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits: Failures in Flash reading may occur (sense amplifier perturbation). Refer to next Figure 44 for a scheme of the input circuitry. 4. Not 100% tested, guaranteed by design characterization. 5. Overload conditions occur if the standard operating conditions are exceeded, that is, the voltage on any pin exceeds the specified range (that is, VOV > VDD + 0.3 V or VOV < -0.3 V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits. 6. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected if they are used for CS output and the open drain function is not enabled. 7. The maximum current may be drawn while the respective signal line remains inactive. 8. The minimum current must be drawn in order to drive the respective signal line active. 9. The power supply currents, ICC1 and ICC2, are function of the operating frequency (fCPU is expressed in MHz). This dependency is illustrated in the Figure 45 below. These parameters are tested at VDDmax and at maximum CPU clock frequency with all outputs disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: This implies I/O current is not considered. The device performs the following actions: - Fetching code from IRAM and XRAM1 (for ICC1) or from all sectors of both IFlash and XFlash (for ICC2), accessing in read and write to both XRAM modules - Watchdog Timer is enabled and regularly serviced - RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles - Four channels of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): No output toggling - Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6) - ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5 - All interrupts generated by XPWM, RTC, Timers and ADC are not serviced 10. The Idle mode supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is illustrated in the Figure 44 below. These parameters are tested and at maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min. 11. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 to 0.1 V or at VDD - 0.1 V to VDD, VAREF = 0 V, all outputs (including pins configured as outputs) disconnected. Furthermore, the Main Voltage Regulator is assumed off: In case it is not, additional 1mA shall be assumed.
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Electrical characteristics Figure 44. Port2 test mode structure
Output Buffer Clock P2.0 CC0IO
ST10F276Z5
Alternate Data Input
Input Latch
Fast External Interrupt Input Test Mode Flash Sense Amplifier and Column Decoder For Port2 complete structure refer also to Figure 44.
Figure 45. Supply current versus the operating frequency (RUN and IDLE modes)
150 ICC1 ICC2
100
I [mA]
IID 50
0 0 10 20 30 40 50 60 70 fCPU [MHz]
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Electrical characteristics
23.6
Flash characteristics
VDD = 5 V 10%, VSS = 0 V Table 93. Flash characteristics
Typical TA = 25 C 0 cycles Word program (32-bit)(2) Double word program (64-bit)(2) Bank 0 program (384K) (double word program) Bank 1 program (128K) (double word program) Bank 2 program (192K) (double word program) Bank 3 program (128K) (double word program) Sector erase (8K) Sector erase (32K) Sector erase (64K) Bank 0 erase (384K) (3) Bank 1 erase (128K) (3) Bank 2 erase (192K) (3) Bank 3 erase (128K) (3) I-Module erase (512K)(4) X-Module erase (320K)(4) Chip erase (832K) (5) Recovery from Power-down (tPD) Program suspend latency(6) 35 60 2.9 1.0 1.5 1.0 0.6 0.5 1.1 0.8 1.7 1.3 8.2 5.8 3.0 2.2 4.3 3.1 3.0 2.2 11.2 7.6 7.3 4.9 18.5 12.0 - -
(1)
Parameter
Maximum TA = 125 C 0 cycles 80 150 7.4 2.5 3.7 2.5 0.9 0.8 2.0 1.8 3.7 3.3 20.2 17.7 7.0 6.2 10.3 9.1 7.0 6.2 27.2 23.5 17.3 14.8 44.4 37.9 40 10
(1)
Unit
Notes
100k cycles 290 570 28.0 9.3 14.0 9.3 1.0 0.9 2.7 2.5 5.1 4.7 28.6 26.1 9.8 9.0 14.5 13.3 9.8 9.0 38.4 34.7 24.3 21.8 62.6 56.1 40 10 s s s s s s s s s s s s s s s s s s - - - - - - not preprogrammed preprogrammed not preprogrammed preprogrammed not preprogrammed preprogrammed not preprogrammed preprogrammed not preprogrammed preprogrammed not preprogrammed preprogrammed not preprogrammed preprogrammed not preprogrammed preprogrammed not preprogrammed preprogrammed not preprogrammed preprogrammed
(6)
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Electrical characteristics Table 93. Flash characteristics (continued)
Typical TA = 25 C 0 cycles Erase suspend latency Erase suspend request Rate (6) Set protection (6)
(6) (1)
ST10F276Z5
Parameter
Maximum TA = 125 C 0 cycles 30 20 170
(1)
Unit
Notes
100k cycles 30 20 170 s ms s Min delay between two requests
- 20 40
1. The figures are given after about 100 cycles due to testing routines (0 cycles at the final customer). 2. Word and Double Word Programming times are provided as average value derived from a full sector programming time: Absolute value of a Word or Double Word Programming time could be longer than the provided average value. 3. Bank Erase is obtained through a multiple Sector Erase operation (setting bits related to all sectors of the Bank). 4. Module Erase is obtained through a sequence of two Bank Erase operations (since each module is composed by two Banks). 5. Chip Erase is obtained through a sequence of two Module Erase operations on I- and X-Module. 6. Not 100% tested, guaranteed by design characterization
Table 94.
.
Data retention characteristics
Data retention time (average ambient temperature 60 C) 832 Kbyte (code store) > 20 years 64 Kbyte (EEPROM emulation)(1) > 20 years > 20 years 10 years 1 year
Number of program / erase cycles (-40 C TA 125 C) 0 - 100 1000 10000 100000
1. Two 64 Kbyte Flash Sectors may be typically used to emulate up to 4, 8 or 16 Kbytes of EEPROM. Therefore, in case of an emulation of a 16 Kbyte EEPROM, 100000 Flash Program / Erase cycles are equivalent to 800000 EEPROM Program/Erase cycles. For an efficient use of the Read While Write feature and/or EEPROM Emulation please refer to dedicated Application Note document (AN2061 - EEPROM Emulation with ST10F2xx). Contact your local field service, local sales person or STMicroelectronics representative to obtain a copy of such a guideline document.
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ST10F276Z5
Electrical characteristics
23.7
A/D converter characteristics
VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C, 4.5 V VAREF VDD, VSS VAGND VSS + 0.2V
Table 95. A/D converter characteristics Limit values Symbol VAREFSR VAGNDSR VAIN SR IAREF CC tS tC
DNL INL OFS
Parameter Analog reference voltage(1) Analog ground voltage Analog Input voltage(2) Reference supply current Sample time Conversion time Differential nonlinearity(6)
Test condition Min. 4.5 VSS VAGND Running mode (3)Power-down mode
(4) (5)
Unit Max. VDD VSS + 0.2 VAREF 5 1 - - +1 +1.5 +1.5 +2.0 +5.0 +7.0 10-6 3 4 6 3.5 600 1600 1300 V V V mA A s s LSB LSB LSB LSB LSB LSB - pF pF pF pF W W W
- - 1 3 -1 -1.5 -1.5 -2.0 -5.0 -7.0 - -
CC CC CC CC CC
No overload No overload No overload Port5 Port1 - No overload(3) Port1 - Overload(3) On both Port5 and Port1
Integral nonlinearity (6) Offset error
(6)
TUE CC
Total unadjusted
error(6)
K
CC
Coupling factor between inputs(3) (7) Input pin capacitance(3) (8)
CP1 CC CP2 CC CS CC Sampling capacitance(3)(8) Analog switch resistance (3)
(8)
Port5 Port1
- -
RSW CC RAD CC
Port5 Port1
- - -
1. VAREF can be tied to ground when A/D converter is not in use: An extra consumption (around 200A) on main VDD is added due to internal analog circuitry not completely turned off. Therefore, it is suggested to maintain the VAREF at VDD level even when not in use, and eventually switch off the A/D converter circuitry setting bit ADOFF in ADCON register. 2. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be 0x000H or 0x3FFH, respectively. 3. Not 100% tested, guaranteed by design characterization. 4. During the sample time, the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming and can be taken from Table 96. 5. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from next Table 96.
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ST10F276Z5
6. DNL, INL, OFS and TUE are tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 5.0 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. "LSB" has a value of VAREF/1024. For Port5 channels, the specified TUE ( 2LSB) is also guaranteed with an overload condition (see IOV specification) occurring on a maximum of 2 not selected analog input pins of Port5 and the absolute sum of input overload currents on all Port5 analog input pins does not exceed 10 mA. For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins: When an overload condition occurs on a maximum of 2 not selected analog input pins of Port1 and the input positive overload current on all analog input pins does not exceed 10 mA (either dynamic or static injection), the specified TUE is degraded ( 7LSB). To obtain the same accuracy, the negative injection current on Port1 pins shall not exceed -1mA in case of both dynamic and static injection. 7. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channels with the overload current within the different specified ranges (for both positive and negative injection current). 8. Refer to scheme shown in Figure 47.
23.7.1
Conversion timing control
When a conversion starts, first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. The time to load the capacitances is referred to as sample time. Next, the sampled voltage is converted in several successive steps into a digital value, which corresponds to the 10-bit resolution of the ADC. During these steps the internal capacitances are repeatedly charged and discharged via the VAREF pin. The current that must be drawn from the sources for sampling and changing charges depends on the duration of each step because the capacitors must reach their final voltage level within the given time, at least with a certain approximation. However, the maximum current that a source can deliver depends on its internal resistance. The time that the two different actions take during conversion (sampling and converting) can be programmed within a certain range in the device relative to the CPU clock. The absolute time consumed by the different conversion steps is therefore independent from the general speed of the controller. This allows adjusting the device A/D converter to the properties of the system: Fast conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. However, the internal resistance of analog source and analog supply must be sufficiently low. High internal resistance can be achieved by programming the respective times to a higher value or to the possible maximum. This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible. However, the conversion rate in this case may be considerably lower. The conversion times are programmed via the upper 4 bits of register ADCON. Bit fields ADCTC and ADSTC define the basic conversion time and in particular the partition between the sample phase and comparison phases. The table below lists the possible combinations. The timings refer to the unit TCL, where fCPU = 1/2TCL. A complete conversion time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register. Table 96.
ADCTC 00 00
A/D Converter programming
ADSTC 00 01 Sample TCL * 120 TCL * 140 Comparison TCL * 240 TCL * 280 Extra TCL * 28 TCL * 16 Total conversion TCL * 388 TCL * 436
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ADCTC 00 00 11 11 11 11 10 10 10 10
Electrical characteristics A/D Converter programming (continued)
ADSTC 10 11 00 01 10 11 00 01 10 11 Sample TCL * 200 TCL * 400 TCL * 240 TCL * 280 TCL * 400 TCL * 800 TCL * 480 TCL * 560 TCL * 800 TCL * 1600 Comparison TCL * 280 TCL * 280 TCL * 480 TCL * 560 TCL * 560 TCL * 560 TCL * 960 TCL * 1120 TCL * 1120 TCL * 1120 Extra TCL * 52 TCL * 44 TCL * 52 TCL * 28 TCL * 100 TCL * 52 TCL * 100 TCL * 52 TCL * 196 TCL * 164 Total conversion TCL * 532 TCL * 724 TCL * 772 TCL * 868 TCL * 1060 TCL * 1444 TCL * 1540 TCL * 1732 TCL * 2116 TCL * 2884
Note:
The total conversion time is compatible with the formula valid for ST10F269, while the meaning of the bit fields ADCTC and ADSTC is no longer compatible: The minimum conversion time is 388 TCL, which at 40 MHz CPU frequency corresponds to 4.85s (see ST10F269).
23.7.2
A/D conversion accuracy
The A/D converter compares the analog voltage sampled on the selected analog input channel to its analog reference voltage (VAREF) and converts it into 10-bit digital data. The absolute accuracy of the A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors: - - - - Offset error (OFS) Gain error (GE) Quantization error Nonlinearity error (differential and integral)
These four error quantities are explained below using Figure 46.
Offset error
Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) 00 to 01 (Figure 46, see OFS).
Gain error
Gain error is the deviation between the actual and ideal A/D conversion characteristics when the digital output value changes from the 3FE to the maximum 3FF, once offset error is subtracted. Gain error combined with offset error represents the so-called full-scale error (Figure 46, OFS + GE).
Quantization error
Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB.
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Nonlinearity error
Nonlinearity error is the deviation between actual and the best-fitting A/D conversion characteristics (see Figure 46): - - Differential nonlinearity error is the actual step dimension versus the ideal one (1 LSBIDEAL). Integral nonlinearity error is the distance between the center of the actual step and the center of the bisector line, in the actual characteristics. Note that for integral nonlinearity error, the effect of offset, gain and quantization errors is not included.
Note:
Bisector characteristic is obtained drawing a line from 1/2 LSB before the first step of the real characteristic, and 1/2 LSB after the last step again of the real characteristic.
23.7.3
Total unadjusted error
The total unadjusted error (TUE) specifies the maximum deviation from the ideal characteristic: The number provided in the datasheet represents the maximum error with respect to the entire characteristic. It is a combination of the offset, gain and integral linearity errors. The different errors may compensate each other depending on the relative sign of the offset and gain errors. Refer to Figure 46, see TUE. Figure 46. A/D conversion characteristic
Offset error OFS
3FF 3FE
Gain error GE
(6)
3FD
Ideal characteristic
3FC 3FB 3FA
(2) Digital 007 out (HEX)
006 005
Bisector characteristic (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential Nonlinearity Error (DNL) (4) Integral Nonlinearity Error (INL) (5) Center of a step of the actual transfer curve (6) Quantization Error (1/2 LSB) (7) Total Unadjusted Error (TUE)
(7)
(1)
(5)
004 003 002 001 000 1 2 3 4 5 6 7 1018 1020 1022
(4) (3) 1 LSB (ideal)
1024
Offset error OFS
VAIN (LSBIDEAL) [LSBIDEAL = VAREF / 1024]
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23.7.4
Analog reference pins
The accuracy of the A/D converter depends on the accuracy of its analog reference: A noise in the reference results in proportionate error in a conversion. A low pass filter on the A/D converter reference source (supplied through pins VAREF and VAGND), is recommended in order to clean the signal, minimizing the noise. A simple capacitive bypassing may be sufficient in most cases; in presence of high RF noise energy, inductors or ferrite beads may be necessary. In this architecture, VAREF and VAGND pins also represent the power supply of the analog circuitry of the A/D converter: There is an effective DC current requirement from the reference voltage by the internal resistor string in the R-C DAC array and by the rest of the analog circuitry. An external resistance on VAREF could introduce error under certain conditions: For this reasons, series resistance is not advisable and more generally, any series devices in the filter network should be designed to minimize the DC resistance.
23.7.5
Analog input pins
To improve the accuracy of the A/D converter, analog input pins must have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: The capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; moreover, its source charges during the sampling phase, when the analog signal source is a high-impedance source. A real filter is typically obtained by using a series resistance with a capacitor on the input pin (simple RC Filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth). Figure 47. A/D converter input pins scheme
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source RS Filter RF Current Limiter RL Channel Selection RSW
Sampling
RAD
VA
CF
CP1
CP2
CS
RS RF CF RL RSW RAD cp CS
Source impedance Filter resistance Filter capacitance Current limiter resistance Channel selection switch impedance Sampling switch impedance Pin capacitance (two contributions, CP1 and CP2) Sampling capacitance
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Input leakage and external circuit
The series resistor utilized to limit the current to a pin (see RL in Figure 47), in combination with a large source impedance, can lead to a degradation of A/D converter accuracy when input leakage is present. Data about maximum input leakage current at each pin is provided in the datasheet (Electrical Characteristics section). Input leakage is greatest at high operating temperatures and in general decreases by one half for each 10 C decrease in temperature. Considering that, for a 10-bit A/D converter one count is about 5mV (assuming VAREF = 5 V), an input leakage of 100nA acting though an RL = 50k of external resistance leads to an error of exactly one count (5mV); if the resistance were 100k, the error would become two counts. Eventual additional leakage due to external clamping diodes must also be taken into account in computing the total leakage affecting the A/D converter measurements. Another contribution to the total leakage is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of a single channel (maximum when fixed channel continuous conversion mode is selected), it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 250 kHz, with CS equal to 4 pF, a resistance of 1M is obtained (REQ = 1 / fCCS, where fC represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the following relation:
R S + R F + R L + R SW + R AD 1 -V A ----------------------------------------------------------------------------- < -- LSB R EQ 2
The formula above places constraints on external network design, in particular on resistive path. A second aspect involving the capacitance network must be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit shown in Figure 47), when the sampling phase is started (A/D switch close), a charge sharing phenomena is installed. Figure 48. Charge sharing timing diagram during sampling phase
VCS VA VA2 1 2 1 < (RSW + RAD) CS << TS VA1 2 = RL (CS + CP1 + CP2) Voltage Transient on CS
V < 0.5 LSB
TS
t
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In particular two different transient periods can be distinguished (see Figure 48): 1. A first and quick charge transfer from the internal capacitances CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): Considering a worst case (since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series and the time constant is:
CP CS 1 = ( R SW + R AD ) ---------------------CP + CS
This relation can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to also be robust in the very worst case: The sampling time TS is always much longer than the internal time constant:
1 < ( R SW + R AD ) * C S T S
The charge of CP1 and CP2 is also redistributed on CS, determining a new value of the voltage VA1 on the capacitance according to the following equation:
V A1 ( C S + C P1 + C P2 ) = V A ( C P1 + C P2 )
2.
A second charge transfer also involves CF (that is typically bigger than the on-chip capacitance) through the resistance RL: Again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is:
2 < R L ( C S + C P1 + C P2 )
In this case, the time constant depends on the external circuit: In particular, imposing that the transient is completed well before the end of sampling time TS, a constraint on RL sizing is obtained:
0 2 = 10 R L ( C S + C P1 + C P2 ) TS
Of course, RL must also be sized according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being that CF is definitely bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. The following equation must be respected (charge balance assuming now CS already charged at VA1):
VA2 ( C S + C P1 + C P2 + C F ) = V A C F + V A1 ( C P1 + C P2 + C S )
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, cannot provide the extra charge to compensate for the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing (see Figure 49). Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF), according to Nyquist theorem the conversion rate fC must be at least 2f0, meaning that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is
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selected (fastest conversion rate at a specific channel): In conclusion, it is evident that the time constant of the filter RFCF is definitely much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. Figure 49. Anti-aliasing filter and conversion rate
Analog source bandwidth (VA) Noise TC 2 RFCF (Conversion rate vs. filter pole) fF = f0 (Anti-aliasing Filtering Condition) 2 f0 fC (Nyquist)
f0
f
Sampled signal spectrum (fC = conversion Rate)
Anti-aliasing filter (fF = RC Filter pole)
fF
f
f0
fC
f
The considerations above lead to impose new constraints to the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive the following relation between the ideal and real sampled voltage on CS:
VA C P1 + C P2 + C F ----------- = -----------------------------------------------------------V A2 C P1 + C P2 + C F + C S
From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count (~2.44mV), it is immediately evident that a constraint is on CF value:
C F > 2048 C S
The next section provides an example of how to design the external network, based on some reasonable values for the internal parameters and on a hypothesis on the characteristics of the analog signal to be sampled.
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23.7.6
Example of external network sizing
The following hypothesis is formulated in order to proceed with designing the external network on A/D converter input pins:

Analog signal source bandwidth (f0):10 kHz Conversion rate (fC): 25 kHz Sampling time (TS): 1s Pin input capacitance (CP1): 5 pF Pin input routing capacitance (CP2): 1 pF Sampling capacitance (CS): 4 pF Maximum input current injection (IINJ): 3 mA Maximum analog source voltage (VAM): 12 V Analog source impedance (RS): 100 Channel switch resistance (RSW): 500 Sampling switch resistance (RAD): 200 Supposing to design the filter with the pole exactly at the maximum frequency of the signal, the time constant of the filter is:
1 R C C F = ----------- = 15.9s 2f 0
1.
2.
Using the relation between CF and CS and taking some margin (4000 instead of 2048), it is possible to define CF:
C F = 4000 C S = 16nF
3.
As a consequence of Step 1 and 2, RC can be chosen:
1R F = -------------------- = 995 1k 2f 0 C F
4.
Considering the current injection limitation and supposing that the source can go up to 12V, the total series resistance can be defined as:
V AM R S + R F + R L = ------------ = 4k I INJ
from which is now simple to define the value of RL:
V AM R L = ------------ - R F - R S = 2.9k I INJ
Now, the three elements of the external circuit RF, CF and RL are defined. Some conditions discussed in the previous paragraphs have been used to size the component; the others must now be verified. The relation which allows to minimize the accuracy error introduced by the switched capacitance equivalent resistance is in this case:
1 R EQ = -------------- = 10M fC CS
So the error due to the voltage partitioning between the real resistive path and CS is less
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R +R +R +R +R 1 S F L SW AD V ------------------------------------------------------------------------ = 2.35mV < -- LSB A R 2 EQ
ST10F276Z5
The other conditions to verify are if the time constants of the transients are really and significantly shorter than the sampling period duration TS:
1 = ( R SW + R AD ) CS = 2.8ns << TS = 1s 10 = 10R ( C + C + C ) = 290ns < TS = 1s 2 LS P1 P2
For a complete set of parameters characterizing the ST10F276Z5 A/D converter equivalent circuit, refer to A/D Converter Characteristics table at page 187.
23.8
23.8.1
AC characteristics
Test waveforms
Figure 50. Input/output waveforms
2.4 V 2.0 V Test Points 0.8 V 0.8 V 2.0 V
0.4 V
AC inputs during testing are driven at 2.4 V for a logic `1' and 0.4 V for a logic `0'. Timing measurements are made at VIH min. for a logic `1' and VIL max for a logic `0'.
Figure 51. Float waveforms
VOH VLOAD + 0.1 V VLOAD VLOAD - 0.1 V VOH - 0.1 V Timing Reference Points VOL + 0.1 V VOL For timing purposes a port pin is no longer floating when VLOAD changes of 100mV occur. It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA).
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23.8.2
Definition of internal timing
The internal operation of the ST10F276Z5 is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL". The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This influence must be regarded when calculating the timings for the ST10F276Z5. The example for PLL operation shown in Figure 52 refers to a PLL factor of 4. The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). Figure 52. Generation mechanisms for the CPU clock
Phase locked loop operation fXTAL fCPU
TCL TCL
Direct clock drive fXTAL fCPU
TCL TCL
Prescaler operation fXTAL fCPU
TCL TCL
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23.8.3
Clock generation modes
The following table associates the combinations of these 3 bits with the respective clock generation mode. Table 97.
P0.15-13 (P0H.7-5) 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0
On-chip clock generator selections
CPU frequency fCPU = fXTAL x F FXTAL x 4 FXTAL x 3 FXTAL x 8 FXTAL x 5 FXTAL x 1 FXTAL x 10 FXTAL / 2 FXTAL x 16 External clock input range (1)(2) 4 to 8 MHz 5.3 to 10.6 MHz 4 to 8 MHz 6.4 to 12 MHz 1 to 64 MHz 4 to 6.4 MHz 4 to 12 MHz 4 MHz CPU clock via prescaler (3) Direct Drive (oscillator bypassed) (3) Notes Default configuration
1. The external clock input range refers to a CPU clock range of 1...64 MHz. Moreover, the PLL usage is limited to 4-12 MHz input frequency range. All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the internal oscillator amplifier (apart from Direct Drive); on the contrary, the clock can be forced through an external clock source only in Direct Drive mode (on-chip oscillator amplifier disabled, so no crystal or resonator can be used). 2. The limits on input frequency are 4-12 MHz since the usage of the internal oscillator amplifier is required. Also, when the PLL is not used and the CPU clock corresponds to FXTAL/2, an external crystal or resonator must be used: It is not possible to force any clock though an external clock source. 3. The maximum depends on the duty cycle of the external clock signal: When 64 MHz is used, 50% duty cycle shall be granted (low phase = high phase = 7.8 ns); when 32 MHz is selected, a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 7.8ns).
23.8.4
Prescaler operation
When pins P0.15-13 (P0H.7-5) equal `001' during reset, the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (that is, the duration of an individual TCL) is defined by the period of the input clock fXTAL. The timings listed in the AC Characteristics that refer to TCL can therefore be calculated using the period of fXTAL for any TCL. Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
23.8.5
Direct drive
When pins P0.15-13 (P0H.7-5) equal `011' during reset, the on-chip phase locked loop is disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by the input clock signal on XTAL1 pin. The frequency of the CPU clock (fCPU) directly follows the frequency of fXTAL so the high and low time of fCPU (that is, the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL.
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Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value can be calculated by the following formula:
TCL min = 1 f XTALl xlDC min DC = duty cycle
For two consecutive TCLs, the deviation caused by the duty cycle of fXTAL is compensated, so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin is used only once for timings that require an odd number of TCLs (1, 3, ...). Timings that require an even number of TCLs (2, 4, ...) may use the formula:
2TCL = 1 f XTAL
The address float timings in multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL x DCmax) instead of TCLmin. Similarly to what happens for Prescaler Operation, if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
23.8.6
Oscillator watchdog (OWD)
An on-chip watchdog oscillator is implemented in the ST10F276Z5. This feature is used for safety operation with an external crystal oscillator (available only when using direct drive mode with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the frequency of the external crystal oscillator). This watchdog oscillator operates as following. The reset default configuration enables the watchdog oscillator. It can be disabled by setting the OWDDIS (bit 4) of SYSCON register. When the OWD is enabled, the PLL runs at its free-running frequency and it increments the watchdog counter. On each transition of external clock, the watchdog counter is cleared. If an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal is switched to the PLL free-running clock signal and the oscillator watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct clock input. When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply current.
23.8.7
Phase locked loop (PLL)
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and it provides the CPU clock (see Table 97). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (fCPU = fXTAL x F). With every F'th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, so the CPU clock frequency does not change abruptly.
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Due to this adaptation to the input clock, the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to one TCL period. This is especially important for bus cycles using wait states and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (such as, for example, pulse train generation or measurement, lower baud rates) the deviation caused by the PLL jitter is negligible. Refer to next Section 23.8.9: PLL Jitter for more details.
23.8.8
Voltage controlled oscillator
The ST10F276Z5 implements a PLL which combines different levels of frequency dividers with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. The following table presents a detailed summary of the internal settings and VCO frequency. Table 98.
P0.15-13 (P0H.7-5) 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0
Internal PLL divider mechanism
XTAL frequency 4 to 8 MHz 5.3 to 10.6 MHz 4 to 8 MHz Input prescaler FXTAL / 4 FXTAL / 4 FXTAL / 4 PLL Multiply by 64 48 64 40 Divide by 4 4 2 2 Output prescaler - - - - - - FPLL / 2 - CPU frequency fCPU = fXTAL x F FXTAL x 4 FXTAL x 3 FXTAL x 8 FXTAL x 5 FXTAL x 1 FXTAL x 10 FXTAL / 2 FXTAL x 16
6.4 to 12 MHz FXTAL / 4 1 to 64 MHz 4 to 6.4 MHz 4 to 12 MHz 4 MHz - FXTAL / 2 - FXTAL / 2
PLL bypassed 40 2
PLL bypassed 64 2
The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is 64 to 128 MHz. The CPU clock frequency range when PLL is used is 16 to 64 MHz.
Example 1

FXTAL = 10 MHz P0(15:13) = `110' (multiplication by 3) PLL input frequency = 2.5 MHz VCO frequency = 120 MHz PLL output frequency = 30 MHz (VCO frequency divided by 4) FCPU = 30 MHz (no effect of output prescaler)
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Example 2

FXTAL = 8 MHz P0(15:13) = `100' (multiplication by 5) PLL input frequency = 2 MHz VCO frequency = 80 MHz PLL output frequency = 40 MHz (VCO frequency divided by 2) FCPU = 40 MHz (no effect of output prescaler)
23.8.9
PLL Jitter
Two kinds of PLL jitter are defined:
Self referred single period jitter Also called "Period Jitter", it can be defined as the difference of the Tmax and Tmin, where Tmax is the maximum time period of the PLL output clock and Tmin is the minimum time period of the PLL output clock. Self referred long term jitter Also called "N period jitter", it can be defined as the difference of Tmax and Tmin, where Tmax is the maximum time difference between N + 1 clock rising edges and Tmin is the minimum time difference between N + 1 clock rising edges. Here N should be kept sufficiently large to have the long term jitter. For N = 1, this becomes the single period jitter. Jitter in the input clock Noise in the PLL loop
Jitter at the PLL output is caused by:

23.8.10
Jitter in the input clock
PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency jitter (frequency > PLL bandwidth) is attenuated at 20dB/decade.
23.8.11
Noise in the PLL loop
This condition again is attributed to the following sources:

Device noise of the circuit in the PLL Noise in supply and substrate
Device noise of the circuit in the PLL
Long term jitter is inversely proportional to the bandwidth of the PLL: The wider the loop bandwidth, the lower the jitter due to noise in the loop. Moreover, long term jitter is practically independent of the multiplication factor. The most noise sensitive circuit in the PLL circuit is definitely the VCO (Voltage Controlled Oscillator). There are two main sources of noise: Thermal (random noise, frequency independent thus practically white noise) and flicker (low frequency noise, 1/f). For the frequency characteristics of the VCO circuitry, the effect of the thermal noise results in a 1/f2 region in the output noise spectrum, while the flicker noise in a 1/f3. Assuming a noiseless PLL input and supposing that the VCO is dominated by its 1/f2 noise, the R.M.S. value of the accumulated jitter is proportional to the square root of N, where N is the number of clock
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Electrical characteristics
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periods within the considered time interval. On the contrary, assuming again a noiseless PLL input and supposing that the VCO is dominated by its 1/f3 noise, the R.M.S. value of the accumulated jitter is proportional to N, where N is the number of clock periods within the considered time interval. The jitter in the PLL loop can be modelized as dominated by the i1/f2 noise for N smaller than a certain value depending on the PLL output frequency and on the bandwidth characteristics of loop. Above this first value, the jitter becomes dominated by the i1/f3 noise component. Lastly, for N greater than a second value of N, a saturation effect is evident, so the jitter does not grow anymore when considering a longer time interval (jitter stable increasing the number of clock periods N). The PLL loop acts as a high pass filter for any noise in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation value corresponds to what has been called self referred long term jitter of the PLL. In Figure 56 the maximum jitter trend versus the number of clock periods N (for some typical CPU frequencies) is shown: The curves represent the very worst case, computed taking into account all corners of temperature, power supply and process variations; the real jitter is always measured well below the given worst case values.
Noise in supply and substrate
Digital supply noise adds determining elements to PLL output jitter, independent of the multiplication factor. Its effect is strongly reduced thanks to particular care used in the physical implementation and integration of the PLL module inside the device. In any case, the contribution of digital noise to global jitter is widely taken into account in the curves provided in Figure 56. Figure 53. ST10F276Z5 PLL jitter
5
16 MHz 24 MHz 32 MHz 40 MHz 64 MHz
4
Jitter [ns]
3
2
1
TJIT
0 0 200 400 600 800 1000 1200 1400
N (CPU clock periods)
202/239
ST10F276Z5
Electrical characteristics
23.8.12
PLL lock/unlock
During normal operation, if the PLL is unlocked for any reason, an interrupt request to the CPU is generated and the reference clock (oscillator) is automatically disconnected from the PLL input: In this way, the PLL goes into free-running mode, providing the system with a backup clock signal (free running frequency Ffree). This feature allows to recover from a crystal failure occurrence without risking to go into an undefined configuration: The system is provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe mode. The path between the reference clock and PLL input can be restored only by a hardware reset, or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.
Note:
The external RC circuit on RSTIN pin must be the right size in order to extend the duration of the low pulse to grant the PLL to be locked before the level at RSTIN pin is recognized high: Bidirectional reset internally drives RSTIN pin low for just 1024 TCL (definitely not sufficient to get the PLL locked starting from free-running mode). Conditions: VDD = 5 V 10%, TA = -40 / +125 oC Table 99.
Symbol TPSUP TLOCK TJIT Ffree
PLL lock/unlock timing
Value Parameter PLL Start-up time (1) PLL Lock-in time Single Period Jitter (1) (cycle to cycle = 2 TCL) PLL free running frequency Conditions Min. Stable VDD and reference clock Stable VDD and reference clock, starting from free-running mode 6 sigma time period variation (peak to peak) Multiplication factors: 3, 4 Multiplication factors: 5, 8, 10, 16 - - -500 250 500 Max. 300 s 250 +500 2000 4000 ps kHz Unit
1. Not 100% tested, guaranteed by design characterization.
23.8.13
Main oscillator specifications
Conditions: VDD = 5 V 10%, TA = -40 / +125 C Table 100. Main oscillator specifications
Value Symbol gm VOSC VAV tSTUP Parameter Oscillator transconductance Oscillation amplitude (1) Peak to peak Sine wave middle Stable VDD - crystal Stable VDD, resonator Conditions Min. 8 - - - - Typ. 17 VDD - 0.4 VDD / 2 -0.25 3 2 Max. 35 - V - 4 ms 3 mA/V Unit
Oscillation voltage level (1) Oscillator start-up time (1)
1. Not 100% tested, guaranteed by design characterization
203/239
Electrical characteristics Figure 54. Crystal oscillator and resonator connection diagram
ST10F276Z5
XTAL1 XTAL2 XTAL1
ST10F276Z5
ST10F276Z5
XTAL2 Resonator
Crystal
CA
CA
Table 101. Negative resistance (absolute min. value @125oC / VDD = 4.5 V)
CA (pF) 4 MHz 8 MHz 12 MHz 12 460 380 370 15 550 460 420 18 675 540 360 22 800 640 27 840 580 33 1000 39 1180 47 1200 -
The given values of CA do not include the stray capacitance of the package and of the printed circuit board: The negative resistance values are calculated assuming additional 5 pF to the values in the table. The crystal shunt capacitance (C0), the package and the stray capacitance between XTAL1 and XTAL2 pins is globally assumed equal to 4 pF. The external resistance between XTAL1 and XTAL2 is not necessary, since already present on the silicon.
23.8.14
32 kHz Oscillator specifications
Conditions: VDD = 5 V 10%, TA = -40 / +125 C Table 102. 32 kHz Oscillator specifications
Value Symbol Parameter Conditions Min. gm32 VOSC32 VAV32 tSTUP32 Oscillator (1) Oscillation amplitude (2)) Oscillation voltage level
(2)
Unit Typ. 31 17 1.0 0.9 1 Max. 50 30 2.4 V 1.2 5 s A/V 20 8 0.5 0.7 -
Start-up Normal run Peak to peak Sine wave middle Stable VDD
Oscillator start-up time(2)
1. At power-on a high current biasing is applied for faster oscillation start-up. Once the oscillation is started, the current biasing is reduced to lower the power consumption of the system. 2. Not 100% tested, guaranteed by design characterization.
204/239
ST10F276Z5 Figure 55. 32 kHz crystal oscillator connection diagram
Electrical characteristics
ST10F276 XTAL3 XTAL4 Crystal CA CA
Table 103. Minimum values of negative resistance (module)
CA = 6 pF CA = 12 pF CA = 15 pF CA = 18 pF CA = 22 pF CA = 27 pF CA = 33 pF 32 kHz 150 k 120 k 90 kW
The given values of CA do not include the stray capacitance of the package and of the printed circuit board: The negative resistance values are calculated assuming additional 5 pF to the values in the table. The crystal shunt capacitance (C0), the package and the stray capacitance between XTAL3 and XTAL4 pins is globally assumed equal to 4 pF. The external resistance between XTAL3 and XTAL4 is not necessary, since already present on the silicon.
Warning:
Direct driving on XTAL3 pin is not supported. Always use a 32 kHz crystal oscillator.
23.8.15
External clock drive XTAL1
When Direct Drive configuration is selected during reset, it is possible to drive the CPU clock directly from the XTAL1 pin, without particular restrictions on the maximum frequency, since the on-chip oscillator amplifier is bypassed. The speed limit is imposed by internal logic that targets a maximum CPU frequency of 64 MHz. In all other clock configurations (Direct Drive with Prescaler or PLL usage) the on-chip oscillator amplifier is not bypassed, so it determines the input clock speed limit. Then an external clock source can be used but limited in the range of frequencies defined for the usage of crystal and resonator (refer also to Table 97 on page 198). External clock drive timing conditions: VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C
205/239
Electrical characteristics Table 104. External clock drive timing
Direct drive fCPU = fXTAL Min. tOSCSR t1 SR t2 SR t3 SR t4 SR XTAL1 period(1) (2) High time
(3)
ST10F276Z5
Symbol
Parameter
Direct drive with prescaler fCPU = fXTAL / 2 Min. 83.3 3 Max. 250 -
PLL usage fCPU = fXTAL x F Min. 83.3 6 Max. 250 -
Unit
Max. - -
15.625 6
Low time(3) Rise time
(3)
ns - 2 - 2 - 2
Fall time(3)
1. The minimum value for the XTAL1 signal period is considered as the theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 2. 4-12 MHz is the input frequency range when using an external clock source. 64 MHz can be applied with an external clock source only when Direct Drive mode is selected: In this case, the oscillator amplifier is bypassed so it does not limit the input frequency. 3. The input clock signal must reach the defined levels VIL2 and VIH2.
Figure 56. External clock drive XTAL1
t1 VIH2 VIL2 t2 tOSC t3 t4
Note:
When Direct Drive is selected, an external clock source can be used to drive XTAL1. The maximum frequency of the external clock source depends on the duty cycle: When 64 MHz is used, 50% duty cycle is granted (low phase = high phase = 7.8 ns); when for instance 32 MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 7.8 ns).
23.8.16
Memory cycle variables
The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes how these variables are computed. Table 105. Memory cycle variables
Symbol tA tC tF Description ALE extension Memory cycle time wait states Memory tri-state time TCL x [ALECTL] 2TCL x (15 - [MCTC]) 2TCL x (1 - [MTTC]) Values
206/239
ST10F276Z5
Electrical characteristics
23.8.17
External memory bus timing
In the next sections the External Memory Bus timings are described. The given values are computed for a maximum CPU clock of 40 MHz. It is evident that when higher CPU clock frequency is used (up to 64 MHz), some numbers in the timing formulas become zero or negative, which in most cases is not acceptable or meaningful. In these cases, the speed of the bus settings tA, tC and tF must be correctly adjusted.
Note:
All External Memory Bus Timings and SSC Timings presented in the following tables are given by design characterization and not fully tested in production.
207/239
Electrical characteristics
ST10F276Z5
23.8.18
Multiplexed bus
VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C, CL = 50 pF, ALE cycle time = 6 TCL + 2tA + tC + tF (75 ns at 40 MHz CPU clock without wait states).
Table 106. Multiplexed bus
Symbol Parameter Unit ns FCPU = 40 MHz TCL = 12.5 ns Min. t5 t6 t7 t8 CC CC CC CC ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay)(1)
- 4 + tA 1.5 + tA 4 + tA 4 + tA -
Variable CPU clock 1/2 TCL = 1 to 64 MHz Min.
TCL - 8.5 + tA TCL - 11 + tA TCL - 8.5 + tA TCL - 8.5 + tA -
Max.
Max.
t9
CC
- 8.5 + tA
- 8.5 + tA
t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t22 t23 t25 t27
CC CC CC CC SR SR SR SR SR SR CC CC CC CC
6 - 18.5
6
Address float after RD, WR (no RW-delay)1 RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address/Unlatched CS to valid data in Data hold after RD rising edge Data float after RD1 Data valid to WR Data hold after WR ALE rising edge after RD, WR Address/Unlatched CS hold after RD, WR
0 - 10 + tC 4 + tF 15 + tF 10 + tF 15.5 + tC
TCL + 6
2TCL - 9.5 + tC - - 3TCL - 9.5 + tC 6 + tC 18.5 + tC 2TCL - 19 + tC 3TCL - 19 + tC - 17.5 + + tA + tC 20 + 2tA + + tC - 16.5 + tF 0 - 2TCL - 15 + tC 2TCL - 8.5 + tF - 2TCL - 10 + tF 2TCL - 15 + tF - 3TCL - 20 + + tA + t C 4TCL - 30 + + 2tA + tC - 2TCL - 8.5 + tF
28 + tC
-
208/239
ST10F276Z5 Table 106. Multiplexed bus (continued)
Symbol Parameter
Electrical characteristics
Min. t38 t39 t40 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t54 t56 CC SR CC CC CC CC CC SR SR CC CC CC SR SR CC CC ALE falling edge to Latched CS Latched CS low to valid data In Latched CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay)1 Address float after RdCS, WrCS (no RW delay)
- - 4 - tA -
Max.
10 - tA 16.5 + tC+ 2tA
Min.
- 4 - tA -
Max.
10 - tA 3TCL- 21+ tC+ 2tA
27 + tF 7 + tA - 5.5 + tA 1.5 -
3TCL - 10.5 + tF TCL - 5.5 + tA - 5.5 + tA 1.5 -
14 - 4 + tC 16.5 + tC 15.5 + tC 28 + tC 10 + tC 0 - 16.5 + tF 2TCL - 9.5 + tC 3TCL - 9.5 + tC 2TCL - 15 + tC 0 -
TCL + 1.5
RdCS to valid data In (with RW delay) RdCS to valid data In (no RW delay) RdCS, WrCS low time (with RW delay) RdCS, WrCS low time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS
(1)
ns
2TCL - 21 + tC 3TCL - 21 + tC
-
-
2TCL - 8.5 + tF
6 + tF
-
2TCL - 19 + tF
-
1. Partially tested, guaranteed by design characterization.
209/239
Unit
FCPU = 40 MHz TCL = 12.5 ns
Variable CPU clock 1/2 TCL = 1 to 64 MHz
Electrical characteristics Figure 57. Multiplexed bus with/without R/W delay and normal ALE
CLKOUT
ST10F276Z5
t5
ALE
t16
t25
t6
t38
t17
t40 t39 t27
CSx
t6
A23-A16 (A15-A8) BHE
t17
Address
t27
t16
Read cycle Address/Data Bus (P0)
t6m
Address
t7
Data In
t18
Address
t8
RD
t10 t14 t12
t19
t13 t9 t11 t15
Write cycle Address/Data Bus (P0)
Address
t23
Data Out
t8
WR WRL WRH
t22 t12 t13
t9
210/239
ST10F276Z5
Electrical characteristics
Figure 58. Multiplexed bus with/without R/W delay and extended ALE
CLKOUT
t5
ALE
t16
t25
t6
t38 t17 t39 t27
t40
CSx
t6
A23-A16 (A15-A8) BHE
t17
Address
t27
Read cycle Address/Data Bus (P0)
t6
Address
t7
Data In
t8 t9
RD
t10 t11 t14 t15 t12 t13
t18 t19
Write cycle Address/Data Bus (P0) Address Data Out
t23 t8 t9
WR WRL WRH
t10 t11
t22
t13
t12
211/239
Electrical characteristics
ST10F276Z5
Figure 59. Multiplexed bus, with/without R/W delay, normal ALE, R/W CS
CLKOUT
t5
ALE
t16
t25
t6
A23-A16 (A15-A8) BHE
t17
Address
t27
t16
Read cycle Address/Data Bus (P0)
t6
Address
t7
t51
Data In Address
t42
RdCSx
t44 t46 t48
t52
t49 t43
Write cycle Address/Data Bus (P0) Address
t45 t47 t56
Data Out
t42
WrCSx
t50 t48 t49
t43
212/239
ST10F276Z5
Electrical characteristics
Figure 60. Multiplexed bus, with/without R/ W delay, extended ALE, R/W CS
CLKOUT
t5
ALE
t16
t25
t6
A23-A16 (A15-A8) BHE
t17
Address
t54
Read cycle Address/Data Bus (P0)
t6
Address
t7
Data In
t42 t43
RdCSx
t44 t45 t46 t48 t47 t49
t18 t19
Write cycle Address/Data Bus (P0) Address Data Out
t42 t43
WrCSx
t44 t45 t50
t56
t48 t49
213/239
Electrical characteristics
ST10F276Z5
23.8.19
Demultiplexed bus
VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C, CL = 50 pF, ALE cycle time = 4 TCL + 2tA + tC + tF (50 ns at 40 MHz CPU clock without wait states). Table 107. Demultiplexed bus
Symbol Parameter Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns FCPU = 40 MHz TCL = 12.5 ns Min. t5 t6 t80 CC ALE high time CC Address setup to ALE Address/Unlatched CS CC setup to RD, WR (with RW-delay) Address/Unlatched CS CC setup to RD, WR (no RW-delay) CC CC SR SR RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) 4 + tA 1.5 + tA 12.5 + 2tA Max. - - - Variable CPU clock 1/2 TCL = 1 to 64 MHz Min. TCL - 8.5 + tA TCL - 11 + tA 2TCL - 12.5 + 2tA Max. - - -
t81
0.5 + 2tA
-
TCL - 12 + 2tA
-
t12 t13 t14 t15 t16 t17 t18
15.5 + tC 28 + tC - - - - 0
- - 6 + tC 18.5 + tC 17.5 + tA + tC 20 + 2tA + tC -
2TCL - 9.5 + tC 3TCL - 9.5 + tC - - - - 0
- - 2TCL - 19 + tC 3TCL - 19 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 8.5 + tF + 2tA TCL - 8.5 + tF + 2tA - - - - -
SR ALE low to valid data in SR SR Address/Unlatched CS to valid data in Data hold after RD rising edge
t20
Data float after RD SR rising edge (with RW-delay)3(1) Data float after RD SR rising edge (no RWdelay) 1 CC Data valid to WR CC Data hold after WR CC CC ALE rising edge after RD, WR Address/Unlatched CS hold after RD, WR (2) Address/Unlatched CS hold after WRH
-
16.5 + tF
-
t21 t22 t24 t26 t28
- 10 + tC 4 + tF -10 + tF 0 + tF - 5 + tF
4 + tF - - - - -
- 2TCL - 15 + tC TCL - 8.5 + tF -10 + tF 0 + tF - 5 + tF
t28h CC
214/239
ST10F276Z5 Table 107. Demultiplexed bus (continued)
Symbol Parameter
Electrical characteristics
Min. t38 t39 t41 CC SR CC ALE falling edge to Latched CS Latched CS low to Valid Data In Latched CS hold after RD, WR - 4 - tA - 2 + tF
Max. 6 - tA 16.5 + tC + 2tA -
Min. - 4 - tA - TCL - 10.5 + tF 2TCL - 11 + 2tA TCL -10.5 + 2tA - - 2TCL - 9.5 + tC 3TCL - 9.5 + tC 2TCL - 15 + tC 0 - - - 8.5 + tF TCL - 10.5 + tF
Max. 6 - tA 3TCL - 21+ tC + 2tA - ns ns ns
t82
Address setup to CC RdCS, WrCS (with RW-delay) Address setup to CC RdCS, WrCS (no RW-delay) SR SR CC CC RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS low time (with RW-delay) RdCS, WrCS low time (no RW-delay)
14 + 2tA
-
-
ns
t83
2 + 2tA
-
-
ns
t46 t47 t48 t49 t50 t51 t53 t68 t55 t57
- - 15.5 + tC 28 + tC 10 + tC 0 - - - 8.5 + tF 2 + tF
4 + tC 16.5 + tC - - - - 16.5 + tF 4 + tF - -
2TCL - 21 + tC 3TCL - 21 + tC - - - - 2TCL - 8.5 + tF TCL - 8.5 + tF - -
ns ns ns ns ns ns ns ns ns ns
CC Data valid to WrCS SR Data hold after RdCS SR SR CC Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after RdCS, WrCS
CC Data hold after WrCS
1. RW-delay and tA refer to the next following bus cycle. 2. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes which occur before the end of RD have no impact on read cycles.
1 Partially tested, guaranteed by design characterization.
The following figures (Figure 57 to Figure 64) present the different configurations of external memory cycle.
215/239
Unit
FCPU = 40 MHz TCL = 12.5 ns
Variable CPU clock 1/2 TCL = 1 to 64 MHz
Electrical characteristics
ST10F276Z5
Figure 61. Demultiplexed bus, with/without read/write delay and normal ALE
CLKOUT
t5
ALE
t16
t26
t6 t38 t17 t39 t6
A23-A16 A15-A0 (P1) BHE
t41 t41u1)
CSx
t17
Address
t28 (or t28h)
Read cycle Data Bus (P0) (D15-D8) D7-D0
t18
Data In
1) Un-latched CSx = t41u = t41 TCL =10.5 + tF.
t80 t81
RD
t14 t15
t20 t21
t12 t13
Write cycle Data Bus (P0) (D15-D8) D7-D0 Data Out
t80 t81
WR WRL WRH
t22
t24
t12 t13
216/239
ST10F276Z5
Electrical characteristics
Figure 62. Demultiplexed bus with/without R/W delay and extended ALE
CLKOUT
t5
ALE
t16
t26
t6 t38 t17 t39
CSx
t41 t28
t6
A23-A16 A15-A0 (P1) BHE
t17
Address
t28
Read cycle Data Bus (P0) (D15-D8) D7-D0
t18
Data In
t80 t81 t15
t14 t21
t20
RD
t12 t13
Write cycle Data Bus (P0) (D15-D8) D7-D0 Data Out
t80 t81
WR WRL WRH
t22
t24
t12 t13
217/239
Electrical characteristics Figure 63. Demultiplexed bus with ALE and R/W CS
ST10F276Z5
CLKOUT
t5
ALE
t16
t26
t6
A23-A16 A15-A0 (P1) BHE
t17
Address
t55
Read cycle Data Bus (P0) (D15-D8) D7-D0
t51
Data In
t82 t83
t46 t47
t53 t68
RdCSx
t48 t49
Write cycle Data Bus (P0) (D15-D8) D7-D0 Data Out
t82 t83
WrCSx
t50
t57
t48 t49
218/239
ST10F276Z5
Electrical characteristics
Figure 64. Demultiplexed bus, no R/W delay, extended ALE, R/W CS
CLKOUT
t5
ALE
t16
t26
t6
A23-A16 A15-A0 (P1) BHE
t17
Address
t55
Read cycle Data Bus (P0) (D15-D8) D7-D0
t51
Data In
t82 t83
RdCSx
t46 t47 t68
t53
t48 t49
Write cycle Data Bus (P0) (D15-D8) D7-D0 Data Out
t82 t83
WrCSx
t50
t57
t48 t49
219/239
Electrical characteristics
ST10F276Z5
23.8.20
CLKOUT and READY
VDD = 5 V 10%, VSS = 0 V, TA = -40 to + 125 C, CL = 50 pF
Table 108. CLKOUT and READY
Symbol Parameter Unit ns FCPU = 40 MHz TCL = 12.5 ns Min. t29 CC t30 CC t31 CC t32 CC t33 CC t34 CC t35 SR t36 SR t37 SR t58 SR t59 SR CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time - CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time (1) Asynchronous READY hold time(1) Async. READY hold time after RD, WR high (Demultiplexed Bus)(2) - 2 + tA 17 2 35 17 2 - 8 + tA - 2 + tA 17 2 2TCL + 10 17 2 - 8 + tA 4 - 4 25 9 - 10 TCL - 2.5 Max. 25 Variable CPU clock 1/2 TCL = 1 to 64 MHz Min. 2TCL TCL - 3.5 - Max. 2TCL
t60 SR
0
2tA + tC + tF
0
2tA + tC + tF
1. These timings are given for characterization purposes only, in order to assure recognition at a specific clock edge. 2. Demultiplexed bus is the worst case. For multiplexed bus 2TCLs must be added to the maximum values. This adds even more time for deactivating READY. 2tA and tC refer to the next following bus cycle and tF refers to the current bus cycle.
220/239
ST10F276Z5 Figure 65. CLKOUT and READY
Running cycle 1) READY wait state
Electrical characteristics
MUX / Tri-state 6)
CLKOUT
t32 t30 t34
t33 t29
t31
ALE
7)
RD, WR
2)
Synchronous
t35
t36
t35
3)
t36
READY
Asynchronous
3)
t58
3)
t59
t58
3)
t59
t60 4)
READY
t37
5)
6)
1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (for example, because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed if READY is removed in response to the command (see Note 4). 6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here. For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles; for a demultiplexed bus without MTTC wait state this delay is zero. 7. The next external bus cycle may start here.
221/239
Electrical characteristics
ST10F276Z5
23.8.21
External bus arbitration
VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C, CL = 50 pF
Table 109. External bus arbitration
Symbol Parameter Unit ns 20 -4
1
FCPU = 40 MHz TCL = 12.5 ns Min. Max. -
Variable CPU Clock 1/2 TCL = 1 to 64 MHz Min. 18.5 Max. -
t61 SR t62 CC t63 CC t64 CC t65 CC t66 CC t67 CC
HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay
18.5
12.5 CLKOUT to HLDA low or BREQ high delay CSx release 1 CSx drive Other signals release Other signals drive - -
12.5
20 -4 - -4 15 20 15
15 20 15
- -4
Figure 66. External bus arbitration (releasing the bus)
CLKOUT
t61
HOLD
t63
(1)
HLDA
t62
BREQ
2)
t64
CSx (P6.x)
1)
3)
t66
Others
1. The device completes the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t64.
222/239
ST10F276Z5 Figure 67. External bus arbitration (regaining the bus)
CLKOUT
Electrical characteristics
2)
t61
HOLD
t62
HLDA
t62
BREQ
t62 1)
t63
t65
CSx (On P6.x)
t67
Other signals
1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the device requesting the bus. 2. The next driven bus cycle may start here.
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Electrical characteristics
ST10F276Z5
23.8.22
High-speed synchronous serial interface (SSC) timing modes
Master mode
VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C, CL = 50 pF Table 110. Master mode
Max. baud rate 6.6MBd (1) @FCPU = 40 MHz ( = 0002h) Min. t300 t301 t302 t303 t304 t305 t306
CC CC CC CC CC
Symbol
Parameter
Variable baud rate ( = 0001h FFFFh) Min. 8TCL t300 / 2 - 12 Max. 262144 TCL -
Unit
Max. 150 -
SSC clock cycle time(2) SSC clock high time
150 63
SSC clock low time SSC clock rise time 10 SSC clock fall time Write data valid after shift edge Write data hold after shift edge 3 Read data setup time before latch edge, phase error detection on (SSCPEN = 1) Read data hold time after latch edge, phase error detection on (SSCPEN = 1) Read data setup time before latch edge, phase error detection off (SSCPEN = 0) Read data hold time after latch edge, phase error detection off (SSCPEN = 0) -2 - 15
10 - 15 -2
CC
CC
t307p
SR
37.5
2TCL + 12.5
ns
t308p
SR
50
-
4TCL
-
t307
SR
25
2TCL
t308
SR
0
0
1. Maximum baud rate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and set to `3h', or with 48 MHz CPU clock and set to `2h'. When 40 MHz CPU clock is used the maximum baud rate cannot be higher than 6.6Mbaud ( = `2h') due to the limited granularity of . Value `1h' for may be used only with CPU clock equal to (or lower than) 32 MHz (after checking that timings are in line with the target slave). 2. Formula for SSC Clock Cycle time: t300 = 4 TCL x ( + 1) Where represents the content of the SSC baud rate register, taken as unsigned 16-bit integer. Minimum limit allowed for t300 is 125 ns (corresponding to 8Mbaud)
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ST10F276Z5 Figure 68. SSC master timing
(1)
t300 t301 t302
Electrical characteristics
(2)
SCLK
t304 t305 t305 1st out bit t307 t308 2nd out bit t307 t303 t306 t305 Last out bit t308
MTSR
MRST
1st in bit
2nd in bit
Last in bit
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received.
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Electrical characteristics
ST10F276Z5
Slave mode
VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C, CL = 50 pF Table 111. Slave mode
Max. baud rate 6.6 MBd(1) @FCPU = 40 MHz ( = 0002h) Min. t310 t311 t312 t313 t314 t315 t316
SR SR SR SR SR
Symbol
Parameter
Variable baud rate ( = 0001h FFFFh) Min. 8TCL t310 / 2 - 12 Max. 262144 TCL -
Unit
Max. 150 -
SSC clock cycle time (2) SSC clock high time
150 63
SSC clock low time SSC clock rise time 10 SSC clock fall time Write data valid after shift edge Write data hold after shift edge Read data setup time before latch edge, phase error detection on (SSCPEN = 1) Read data hold time after latch edge, phase error detection on (SSCPEN = 1) Read data setup time before latch edge, phase error detection off (SSCPEN = 0) Read data hold time after latch edge, phase error detection off (SSCPEN = 0) 0 - 55
10 - 2TCL + 30 0 ns
CC
CC
t317p
SR
62
4TCL + 12
t318p
SR
87
-
6TCL + 12
-
t317
SR
6
6
t318
SR
31
2TCL + 6
1. Maximum baud rate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and set to `3h', or with 48 MHz CPU clock and set to `2h'. When 40 MHz CPU clock is used the maximum baud rate cannot be higher than 6.6Mbaud ( = `2h') due to the limited granularity of . Value `1h' for may be used only with CPU clock lower than 32 MHz (after checking that timings are in line with the target master). 2. Formula for SSC Clock Cycle time: t310 = 4 TCL * ( + 1) Where represents the content of the SSC baud rate register, taken as unsigned 16-bit integer. Minimum limit allowed for t310 is 125ns (corresponding to 8Mbaud).
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ST10F276Z5 Figure 69. SSC slave timing
(1)
1) SCLK
Electrical characteristics
t310
t311
t312
(2)
2)
t314 t315 MRST
1st out bit
t315
2nd out bit
t313 t316
t315
Last out bit
t317 t318
t317 t318
MTSR
1st in bit
2nd in bit
Last in bit
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received.
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Known limitations
ST10F276Z5
24
Known limitations
This section describes the functional and electrical limitations identified on the CEG silicon revision of the ST10F276Z5. The major revision of the device is contained in the device identification register, IDCHIP, located at address F07Ch. For Cxx versions, IDCHIP is set to 1143h.
24.1
Functional limitations
The function limitations identified on the ST10F276Z5 are the following:

Injected conversion stalling the A/D converter (see Section 24.1.1: Injected conversion stalling the A/D converter) Concurrent transmission requests in DAR mode (C-CAN module) (see Section 24.1.2: Concurrent transmission requests in DAR-mode (C-CAN module)) Disabling transmission requests (see Section 24.1.3: Disabling the transmission requests (C-CAN module)) Spurious BREQ pulse in slave mode during external bus arbitration phase (see Section 24.1.4: Spurious BREQ pulse in slave mode during external bus arbitration phase) Executing PWRDN instructions (see Section 24.1.5: Executing PWRDN instructions) Behavior of capture/compare (CAPCOM) outputs in COMPARE mode 3 (see Section 24.1.6: Behavior of CAPCOM outputs in COMPARE mode 3)

24.1.1
Injected conversion stalling the A/D converter
Description
The A/D converter is stalled and no further conversions are performed when a new injection request is issued before the CPU reads the ADDAT2 register (that is when the CPU has not read the result of the previous injection request).
Workarounds and recovery actions
The following actions allow to unlock the A/D converter: 1. 2. Read the ADDAT2 register twice at the end of every injected conversion. This action also prevents the ADC from being stalled. Disable and then enable again the wait for read mode.
Application conditions
This problem occurs if all the following conditions are fulfilled:

Injection requests are hardware triggered (via CapCom CC31). The results of injected conversions are read by performing a PEC transfer. This prevents from reading twice the ADDAT2 register by software. A high level task is disabling the PEC transfer for a long time (time needed for 2 analog conversions plus time between 2 injection requests).
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ST10F276Z5
Known limitations
Therefore, to prevent the locking situation from occurring, it is important to make sure that no task can disable interrupts for a period of time during which 2 injection requests can occur before a read operation is performed.
Detailed analysis
Channel Injection mode allows to convert a specific analog channel without changing the current operating mode. It can also be used when the A/D converter is running in continuous or auto scan mode. The following main points need to be highlighted:

The A/D converter must be in Wait for ADDAT read mode in order for the Channel Injection mode to operate properly. At the end of the injected conversion the data is available in the alternate result register, ADDAT2, and a Channel Injection Complete Interrupt request is generated (ADEIR Flag). If the temporary data register used for ADDAT2 read mode is full, the next conversion (standard or injected) is suspended. The temporary register then stores the content of ADDAT (standard conversion) or ADDAT2 (injected conversion).
If the temporary data register used for ADDAT2 read mode is full and a new injection request occurs, then the new converted value is stored into a temporary data register until the previous one is read from ADDAT2 register. To ensure correct operation as soon as ADDAT2 register is read, the last converted value should be moved from temporary register to ADDAT2 and the ADEINT interrupt should be generated. This allows the CPU to read the last converted value (see Figure 70). In real circumstances, as soon as the ADDAT2 register is read, the last converted value is correctly moved from the temporary register to the ADDAT2, but no ADEINT interrupt request is sent to the Interrupt controller (see Figure 71). As a consequence the CPU/PEC does not know that a new converted value is available in the ADDAT2 register. When the next injection request is issued, the A/D converter fills the temporary register again without generating any ADEINT interrupt request and the converter is stalled. The A/D converter stays in the "wait for read ADDAT2 register" condition forever.
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Known limitations Figure 70. ADC injection theoretical operation
ST10F276Z5
Figure 71. ADC injection actual operation
ADEINT Interrupt not generated ADDAT2 correctly updated and can be read by software
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ST10F276Z5
Known limitations
24.1.2
Concurrent transmission requests in DAR-mode (C-CAN module)
Description
When the C-CAN module is configured to operate in DAR mode (Disable Automatic Retransmission) and the host requests the transmission of several messages at the same time, only two of these messages are transmitted. For all other message transmission requests the TxRqst bits are reset, no transmission is started, and NewDat and IntPnd are kept unchanged. For the two messages which are transmitted, the TxRqst and NewDat bits are reset and IntPnd is set if if it has been enabled by TxIE. TxRqst, NewDat and IntPnd are bits of the message interface control registers. The normal operation mode (DAR = 0) is not affected by this phenomenon.
Workaround
The DAR mode is intended to support time-triggered operation (TTCAN level 1) supporting the transmission of a message only in its dedicated time window. It is an error to request the transmission of several messages at the same time, and no workarounds should consequently be necessary for TTCAN applications. The progress of a requested transmission can be monitored by checking the message object TxRqst and NewDat [optionally IntPnd] bits. In DAR mode, when a message transmission has failed either because the transmission was disturbed or because it has not started, it is necessary to request the message transmission again. For details on DAR mode and message control registers, refer to user manual UM0409.
24.1.3
Disabling the transmission requests (C-CAN module)
Description
If the host disables the pending transmission request of the lowest-priority message (number 32 by default) in the short time window during which the message handler state machine prepares the transmission, but before the transmission has actually started, then this transmission request may remain disabled. It remains in this state even if the host immediately re-enables it. The status of the message object transmission request bit does not show that the transmission is disabled. This only happens when the message object is the only one with a pending transmission request. If the transmission request is blocked in the disabled state, it will be re-enabled by the first activity detected on the CAN bus or by setting the transmission request of any other message object. The other message objects are not affected by this phenomenon.
Workaround
It is usually not necessary to disable the transmission request of a message object. If the message object is to be used for another message, it is sufficient to prepare the new content corresponding to this message in the CPU interface register (Identifier, DLC, Data, with TxRqst and NewDat [optionally TxIE] bits) and to transfer it into the message object. The new content is then transmitted at the next opportunity, and is not altered by a possibly ongoing transmission of the previous content of the same message object.
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Known limitations
ST10F276Z5
24.1.4
Spurious BREQ pulse in slave mode during external bus arbitration phase
Description
Sporadic bus errors may occur when the device operates as a slave and the HOLD signal is used for external bus arbitration. After the slave has been granted the bus, it deactivates sporadically BREQ signal for a short time, even though its access to the bus has not been completed. The master then starts accessing the bus, thus causing a bus conflict between master and slave.
Workaround
To avoid producing any spurious BREQ pulse during slave external bus arbitrations, it is necessary to ensure that the time between the HLDA assertion (Bus Acknowledge from Master device) and the following HOLD falling edge (Bus Request from Master) is longer than three clock cycles. This can be achieved by delaying the HOLD signal with an RC circuit (see Figure 72). Figure 72. Connecting an ST10 in slave mode
HOLD HLDA
BREQ (P6.7) HLDA (P6.6)
BREQ Master VSS
HOLD (P6.5) ST10 in Slave mode
24.1.5
Executing PWRDN instructions
Description
The Power-down mode is not entered and the PWRDN instruction is ignored in the following cases:

The PWRDN instruction is executed while NMI is high (PWDCFG bit of the SYSCON register cleared) The PWRDN instruction is executed while at least one of the Port 2 pins used to exit from Power-down mode (PWDCFG bit of the SYSCON register is set) is at the active level.
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ST10F276Z5
Known limitations
However, in certain cases, the PWRDN instruction is not ignored, no further instructions are fetched from external memory, and the CPU is in a quasi-idle state. This problem only occurs in the following situations: 1. The instructions following the PWRDN instruction are located in an external memory and a multiplexed bus configuration with memory tri-state waitstate (bit MTTCx = 0) is used. The instruction preceding the PWRDN instruction writes to the external memory or to an XPeripheral (such as XRAM or CAN) and the instructions following the PWRDN instruction are located in external memory area. In this case, the problem occurs for all bus configurations.
2.
Note: The on-chip peripherals, such as the watchdog timer, still operate properly. If the watchdog timer is not disabled, it resets the device upon an overflow event. However, interrupts and PEC transfers cannot be processed. Power-down mode is entered if the NMI signal is asserted low while the device is in this quasi-idle state. No problem occurs and the device normally enters Power-down mode if the NMI pin is held low (PWDCFG = 0) or if all Port 2 pins used to exit from Power-down mode are at inactive level (PWDCFG = 1).
Workaround
To prevent this problem from occurring, the PWRDN instruction must be preceded by instructions performing write operations to external memory area or to an XPeripheral. Otherwise, it is recommended to insert a NOP instruction before PWRDN. When using a multiplexed bus with memory tri-state wait state, the PWRDN instruction must be executed from internal RAM or XRAM.
24.1.6
Behavior of CAPCOM outputs in COMPARE mode 3
Description
When a CAPCOM channel is configured in compare mode 3, then the related output level switches to high when the allocated timer, Tx, matches the related CAPCOM register, CCy. When an overflow occurs on the CAPCOM timer Tx, it is reloaded with TxREL content and the output pin is cleared. The output pin level does not change if TxREL and CCy have the same value. The related CAPCOM output stays low when the CAPCOM channel is configured in compare mode 3 and TxREL and Tx related timer registers are loaded with the same value as CCy. This is obtained by executing the following instructions: MOV TxREL, #CCy value x =0,1,7,8 MOV Tx, #CCy value x = 0,1,7,8 MOV TxxCON, #data or bfldl/bfldh TxxCON , #mask, #data i.e. an access is made to the T01CON or T78CON register.
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Known limitations
ST10F276Z5
Workarounds
The following workarounds make the CAPCOM output toggle as expected: 1) Invert the TxREL and Tx configuration as follow: MOV Tx, #CCy value MOV TxREL, #CCy value bfldl/bfldh TxxCON , #mask, #data or MOV TxxCON, #data 2) Insert a NOP instruction before the T01CON or T78CON configuration: MOV Tx, #value MOV TxREL, #value NOP bfldl/bfldh TxxCON , #mask, #data or MOV TxxCON, #data 3) Load the Tx timer with the CCy register minus 1: MOV TxREL, #value MOV Tx, #( value-1) bfldl/bfldh TxxCON , #mask, #data or MOV TxxCON, #data
24.2
Electrical limitations
The PLL lock-time, TLOCK, for x10 multiplication factor is 300 s instead of 250 s (see Table 99).
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ST10F276Z5
Package information
25
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package information
ST10F276Z5
Figure 73. PQFP144 - 144-pin plastic Quad Flatpack 28 x 28 mm, 0.65 mm pitch, package outline
ddd D D1 D3 A1 A A2
108 109
73 72
b
E3
E1
144 1 e 36
37 C L1
E
L
K
7G_ME
Table 112. PQFP144 - 144-pin Plastic Quad Flatpack 28 x 28 mm, 0.65 mm pitch, package mechanical data
millimeters Symbol Typ A A1 A2 b C D D1 D3 e E E1 E3 L L1 K ddd 0.101 31.200 28.000 22.750 0.650 31.200 28.000 22.750 0.800 1.600 0 0.0040 7 0.650 0.950 30.950 27.900 31.450 28.100 3.420 0.250 3.170 0.220 0.130 30.950 27.900 3.670 0.380 0.230 31.450 28.100 1.2283 1.1024 0.8957 0.0256 1.2283 1.1024 0.8957 0.0315 0.0630 0 7 0.0256 0.0374 1.2185 1.0984 1.2382 1.1063 0.1346 Min Max 4.070 0.0098 0.1248 0.0087 0.0051 1.2185 1.0984 0.1445 0.0150 0.0091 1.2382 1.1063 Typ Min Max 0.1602 inches(1)
1. Values in inches are converted from mm and rounded up to 4 decimal places.
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B
ST10F276Z5
Package information
Figure 74. LQFP144 - 144 pin low profile quad flat package 20x20 mm, 0.5 mm pitch, package outline
D D1 D3 A1 108 109 73 72 0.08 mm .003 in. b Seating Plane E A A2
b E3 E1
144 1 e
37 36 c L1
L h
Table 113. LQFP144 - 144 pin low profile quad flat package 20x20mm, 0.5 mm pitch, package mechanical data
mm Dim. Min A A1 A2 b c D D1 D3 E E1 E3 e K L L1 0 0.45 21.80 19.80 0.05 1.35 0.17 0.09 21.80 19.80 22.00 20.00 17.50 22.00 20.00 17.50 0.50 3.5 0.60 1.00 7 0.75 0 0.018 22.20 20.20 0.858 0.780 1.40 0.22 Typ Max 1.60 0.15 1.45 0.27 0.20 22.20 20.20 0.002 0.053 0.007 0.004 0.858 0.780 0.867 0.787 0.689 0.867 0.787 0.689 0.020 3.5 0.024 0.039 7 0.030 0.874 0.795 Min Typ Max 0.063 0.006 0.057 0.011 0.008 0.874 0.795 inches(1)
1. Values in inches are converted from mm and rounded up to 4 decimal places.
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Revision history
ST10F276Z5
26
Revision history
Table 114. Document revision history
Date 02-June-2006 Revision 1 Initial release. Replaced ST10F276 by root part number ST10F276Z5 in datasheet header, Table 1: Device summary and Section 1: Description. Added FB deviation equation in Section 5.3.5: Choosing the baud rate for the BSL via UART. Replaced ST10F273E by ST10F276Z5 in Section 13: A/D converter and Section 20.3: Standby mode. Updated first example in Section 23.8.8: Voltage controlled oscillator. AddedSection 24: Known limitations. Added ECOPACK text in Section 25: Package information. Changes
03-Dec-2007
2
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ST10F276Z5
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